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1. 发明申请

US20090017625A1 Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes 有权
标题翻译： CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US20090017625A1
公开(公告)日：2009-01-15
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , JunJung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

2. 发明授权

US07790622B2 Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes 有权
标题翻译：在CMOS半导体制造工艺中去除栅极侧壁间隔物的方法
公开(公告)号：US07790622B2
公开(公告)日：2010-09-07
申请号：US11778038
申请日：2007-07-14
申请人： Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Jun Jung Kim , Chong Kwang Chang , Min-Chul Sun , Jong Ho Yang , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
摘要翻译：提供半导体制造工艺用于从门结构去除侧壁间隔物，同时减轻或以其他方式预防诸如损坏金属硅化物结构的缺陷机制或以其它方式阻碍或限制后续工艺流程。

3. 发明授权

US07911001B2 Methods for forming self-aligned dual stress liners for CMOS semiconductor devices 有权
标题翻译：用于形成用于CMOS半导体器件的自对准双应力衬垫的方法
公开(公告)号：US07911001B2
公开(公告)日：2011-03-22
申请号：US11778045
申请日：2007-07-15
申请人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
IPC分类号： H01L21/311 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
摘要翻译：提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

4. 发明申请

US20090014808A1 Methods For Forming Self-Aligned Dual Stress Liners For CMOS Semiconductor Devices 有权
标题翻译：用于形成CMOS半导体器件的自对准双重应力衬垫的方法
公开(公告)号：US20090014808A1
公开(公告)日：2009-01-15
申请号：US11778045
申请日：2007-07-15
申请人： Kyoung-Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
发明人： Kyoung-Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
IPC分类号： H01L27/092 , H01L21/311
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
摘要翻译：提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

5. 发明申请

US20110163387A1 METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于形成用于CMOS半导体器件的自对准双应力衬片的方法
公开(公告)号：US20110163387A1
公开(公告)日：2011-07-07
申请号：US13050219
申请日：2011-03-17
申请人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
发明人： Kyoung Woo Lee , Ja Hum Ku , Taehoon Lee , Seung-Man Choi , Thomas W. Dyer
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823871 , H01L29/7843
摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
摘要翻译：提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

6. 发明授权

US07598572B2 Silicided polysilicon spacer for enhanced contact area 失效
标题翻译：用于增强接触面积的硅化多晶硅间隔物
公开(公告)号：US07598572B2
公开(公告)日：2009-10-06
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L29/40
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

7. 发明申请

US20080102612A1 SILICIDED POLYSILICON SPACER FOR ENHANCED CONTACT AREA 失效
标题翻译：用于增强接触面积的多孔聚硅氧烷绝缘子
公开(公告)号：US20080102612A1
公开(公告)日：2008-05-01
申请号：US11552673
申请日：2006-10-25
申请人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Ja-Hum Ku , Yong Meng Lee
IPC分类号： H01L21/44 , H01L21/425 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4983 , H01L21/28123 , H01L21/28518 , H01L21/76897 , H01L21/823418 , H01L21/823481 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
摘要翻译：一种通过形成的硅化多晶硅间隔物具有增加的源/漏接触面积的集成电路器件。形成多晶硅侧壁间隔物，其高度小于所述栅极导体高度的百分之七十，并且在深源极和漏极区域上具有连续的表面硅化物层。接触面积由硅化多晶硅间隔物增强。

8. 发明授权

US07393746B2 Post-silicide spacer removal 失效
标题翻译：后硅化物间隔物去除
公开(公告)号：US07393746B2
公开(公告)日：2008-07-01
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee , JunJung Kim
IPC分类号： H01L21/33
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.
摘要翻译：一种方法在衬底上形成栅极导体，在栅极导体的侧面上形成间隔物（例如，氮化物间隔物），并将杂质注入到未被栅极导体和间隔物保护的衬底的暴露区域中。然后，该方法在衬底的暴露区域的表面上形成硅化物。该方法在硅化物，间隔物和栅极导体之上形成共形保护层（例如，氧化物或其它类似材料）。接下来，该方法在保护层上形成非共形牺牲层（例如，可相对于保护层选择性去除的氮化物或其它材料）。随后的部分蚀刻工艺部分地蚀刻牺牲层，使得在间隔物之上的牺牲层的相对较薄的区域被完全去除，并且除去衬底之上的牺牲层的相对较厚的区域。该方法中的下一步骤仅去除覆盖间隔物的保护层的那些部分，而不去除覆盖硅化物的保护层的部分。由于间隔物现在被暴露并且硅化物被保护层和牺牲层保护，所以该方法可以安全地去除间隔物而不影响硅化物。

9. 发明申请

US20110237039A1 Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions 有权
标题翻译：形成具有SiGe源极/漏极区域的P沟道场效应晶体管的方法
公开(公告)号：US20110237039A1
公开(公告)日：2011-09-29
申请号：US12729486
申请日：2010-03-23
申请人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong-Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅极电极上形成掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

10. 发明授权

US08198194B2 Methods of forming p-channel field effect transistors having SiGe source/drain regions 有权
标题翻译：形成具有SiGe源极/漏极区域的p沟道场效应晶体管的方法
公开(公告)号：US08198194B2
公开(公告)日：2012-06-12
申请号：US12729486
申请日：2010-03-23
申请人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
发明人： Jong Ho Yang , Hyung-rae Lee , Jin-Ping Han , Chung Woh Lai , Henry K. Utomo , Thomas W. Dyer
IPC分类号： H01L21/311
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
摘要翻译：形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。然后在栅电极上图案化掩模层。选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

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