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1. 发明授权

US07989357B2 Method of patterning semiconductor structure and structure thereof 有权
标题翻译：图案化半导体结构及其结构的方法
公开(公告)号：US07989357B2
公开(公告)日：2011-08-02
申请号：US11950741
申请日：2007-12-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L23/48
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

2. 发明授权

US07736966B2 CMOS devices with hybrid channel orientations and method for fabricating the same 有权
标题翻译：具有混合信道取向的CMOS器件及其制造方法
公开(公告)号：US07736966B2
公开(公告)日：2010-06-15
申请号：US11968479
申请日：2008-01-02
申请人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
发明人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a method of fabricating a semiconductor substrate that includes forming at least first and second device regions, wherein the first device region includes a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region includes a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. The semiconductor device structure formed using such a semiconductor substrate includes at least one n-channel field effect transistor (n-FET) formed at the first device region having a channel that extends along the interior surfaces of the first recess, and at least one p-channel field effect transistor (p-FET) formed at the second device region having a channel that extends along the interior surfaces of the second recess.
摘要翻译：本发明涉及一种制造半导体衬底的方法，该方法包括形成至少第一和第二器件区域，其中第一器件区域包括具有沿第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括具有沿着第二不同组的等效晶面取向的内表面的第二凹部。使用这种半导体衬底形成的半导体器件结构包括形成在第一器件区域处的至少一个n沟道场效应晶体管（n-FET），其具有沿着第一凹部的内表面延伸的沟道，并且至少一个p - 沟道场效应晶体管（p-FET），其形成在具有沿着第二凹部的内表面延伸的沟道的第二器件区域处。

3. 发明申请

US20090146221A1 METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF 有权
标题翻译：描绘半导体结构及其结构的方法
公开(公告)号：US20090146221A1
公开(公告)日：2009-06-11
申请号：US11950741
申请日：2007-12-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L27/088 , H01L21/311
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

4. 发明授权

US07456450B2 CMOS devices with hybrid channel orientations and method for fabricating the same 有权
标题翻译：具有混合信道取向的CMOS器件及其制造方法
公开(公告)号：US07456450B2
公开(公告)日：2008-11-25
申请号：US11307481
申请日：2006-02-09
申请人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
发明人： Thomas W. Dyer , Xiangdong Chen , James J. Toomey , Haining S. Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/82385 , H01L21/823857
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region comprises a first recess having interior surfaces oriented along a first set of equivalent crystal planes, and wherein the second device region comprises a second recess having interior surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed at the first device region, which comprises a channel that extends along the interior surfaces of the first recess. At least one p-channel field effect transistor (p-FET) can be formed at the second device region, which comprises a channel that extends along the interior surfaces of the second recess.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底，其中第一器件区域包括具有沿着第一组等效晶面取向的内表面的第一凹槽，并且其中第二器件区域包括第二凹部，沿着第二不同组的等效晶面取向的内表面。可以使用这种半导体衬底形成半导体器件结构。具体而言，可以在第一器件区域形成至少一个n沟道场效应晶体管（n-FET），该第一器件区域包括沿着第一凹槽的内表面延伸的沟道。至少一个p沟道场效应晶体管（p-FET）可以在第二器件区域形成，该第二器件区域包括沿着第二凹槽的内表面延伸的沟道。

5. 发明授权

US07390745B2 Pattern enhancement by crystallographic etching 有权
标题翻译：通过晶体蚀刻的图案增强
公开(公告)号：US07390745B2
公开(公告)日：2008-06-24
申请号：US11162800
申请日：2005-09-23
申请人： Thomas W. Dyer , Kenneth T. Settlemyer, Jr. , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer, Jr. , James J. Toomey , Haining Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

6. 发明授权

US08362531B2 Method of patterning semiconductor structure and structure thereof 有权
标题翻译：图案化半导体结构及其结构的方法
公开(公告)号：US08362531B2
公开(公告)日：2013-01-29
申请号：US13102007
申请日：2011-05-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L29/80
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

7. 发明申请

US20110215437A1 METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF 有权
标题翻译：描绘半导体结构及其结构的方法
公开(公告)号：US20110215437A1
公开(公告)日：2011-09-08
申请号：US13102007
申请日：2011-05-05
申请人： Thomas W. Dyer , James J. Toomey
发明人： Thomas W. Dyer , James J. Toomey
IPC分类号： H01L29/06
CPC分类号： H01L21/8258 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： Method of patterning a semiconductor structure is disclosed. The method involves crystallographic etching techniques to enhance a patterned monocrystalline layer as a hard mask. In one embodiment, the method includes bonding a monocrystalline silicon layer to a non-crystalline protective layer; patterning the monocrystalline layer to form a hard mask; enhancing the pattern of the hard mask; stripping the hard mask after conventional etching of protective layer; and forming a gate oxide thereon. The enhanced patterning of the hard mask is performed with crystallographic etching to replace optical effects of rounding and dimension narrowing at the ends of a defined region with straight edges and sharp corners. A resulting structure from the use of the enhanced patterned hard mask includes a layer of composite materials on the substrate of the semiconductor structure. The layer of composite materials includes different materials in discrete blocks defined by straight edges within the layer.
摘要翻译：公开了图案化半导体结构的方法。该方法涉及晶体蚀刻技术以增强作为硬掩模的图案化单晶层。在一个实施例中，该方法包括将单晶硅层结合到非结晶保护层; 图案化单晶层以形成硬掩模; 增强硬面膜的图案; 常规蚀刻保护层后剥去硬掩模; 并在其上形成栅极氧化物。通过结晶蚀刻来进行硬掩模的增强图案化，以取代在具有直边和锐角的限定区域的端部处的圆化和尺寸变窄的光学效应。使用增强型图案化硬掩模的结果包括在半导体结构的衬底上的复合材料层。复合材料层包括在层内由直边限定的离散块中的不同材料。

8. 发明授权

US07718993B2 Pattern enhancement by crystallographic etching 有权
标题翻译：通过晶体蚀刻的图案增强
公开(公告)号：US07718993B2
公开(公告)日：2010-05-18
申请号：US12108574
申请日：2008-04-24
申请人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
IPC分类号： H01L31/00
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

9. 发明申请

US20080230868A1 PATTERN ENHANCEMENT BY CRYSTALLOGRAPHIC ETCHING 有权
标题翻译：晶体蚀刻的图案增强
公开(公告)号：US20080230868A1
公开(公告)日：2008-09-25
申请号：US12108574
申请日：2008-04-24
申请人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
IPC分类号： H01L29/06
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本上均匀的直边或边缘以及明确限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

10. 发明申请

US20130001660A1 PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 失效
公开(公告)号：US20130001660A1
公开(公告)日：2013-01-03
申请号：US13615955
申请日：2012-09-14
申请人： Thomas W. Dyer
发明人： Thomas W. Dyer
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6656 , H01L21/30608 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/78 , H01L29/7848
摘要： Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

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