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1. 发明授权

US5173623A High performance BiCMOS logic circuits with full output voltage swing up to four predetermined voltage values 失效
标题翻译：具有全输出电压的高性能BiCMOS逻辑电路可摆动多达四个预定电压值
公开(公告)号：US5173623A
公开(公告)日：1992-12-22
申请号：US842801
申请日：1992-02-27
申请人： Kwok K. Chau , James D. Gallia , Ashwin H. Shah
发明人： Kwok K. Chau , James D. Gallia , Ashwin H. Shah
IPC分类号： H03K19/00 , H03K19/0944
CPC分类号： H03K19/0008 , H03K19/09448
摘要： BiCMOS circuits are disclosed which achieve high speed operation under a wide range of loading conditions. The circuits are capable of providing a full output voltage swing and dissipate virtually no static power. The BiCMOS circuits are implemented using both CMOS and bipolar transistors. The circuits use their output signal to control the CMOS transistors that overcome bipolar output drops for full swing operation. The same fundamental CMOS and bipolar configurations can be applied to implement complex and simple logic functions such as NAND, NOR, AND, or OR operations.
摘要翻译：公开了BiCMOS电路，其在宽范围的负载条件下实现高速运行。这些电路能够提供完整的输出电压摆幅并实际上消散静态功率。 BiCMOS电路使用CMOS和双极晶体管实现。这些电路使用它们的输出信号来控制克服双极性输出下降以用于全速操作的CMOS晶体管。可以应用相同的基本CMOS和双极配置来实现复杂和简单的逻辑功能，例如NAND，NOR，AND或OR操作。

2. 发明授权

US4604727A Memory with configuration RAM 失效
标题翻译：内存配置RAM
公开(公告)号：US4604727A
公开(公告)日：1986-08-05
申请号：US528303
申请日：1983-08-31
申请人： Ashwin H. Shah , Pallab K. Chatterjee , James D. Gallia , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , Pallab K. Chatterjee , James D. Gallia , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/417 , G06F11/10 , G06F12/14 , G06F13/28 , G06F13/42 , G11C7/00 , G11C7/24 , G11C11/34 , G11C11/401 , G11C11/41 , G11C11/413 , G11C29/00 , G11C29/42 , H01L21/822 , H01L27/04
CPC分类号： G06F12/1433 , G06F13/28 , G06F13/4243 , G11C7/24 , G06F11/10
摘要： A memory including various selectively configurable peripherals which provide on-chip low-level control features and a configuration RAM storing bits which both provide unclocked full logic-level outputs to control the selectively configurable peripherals and can also be accessed and read out. That is, each cell in the configuration RAM has two output modes: a digital continuous output, which is provided as a continuous control signal to various peripheral circuits and a selectable analog output which is used to read the information stored in the configuration RAM.
摘要翻译：包括提供片上低级控制特征的各种选择性可配置的外围设备的存储器和存储位的配置RAM，它们都提供非锁定的全逻辑电平输出以控制可选择性地配置的外围设备，并且还可被访问和读出。也就是说，配置RAM中的每个单元具有两种输出模式：作为连续控制信号提供给各种外围电路的数字连续输出和用于读取存储在配置RAM中的信息的可选择的模拟输出。

3. 发明授权

US4601019A Memory with redundancy 失效
标题翻译：内存冗余
公开(公告)号：US4601019A
公开(公告)日：1986-07-15
申请号：US528209
申请日：1983-08-31
申请人： Ashwin H. Shah , James D. Gallia , I-Fay Wang , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , James D. Gallia , I-Fay Wang , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/808
摘要： A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.
摘要翻译：具有列冗余的字节宽的内存。冗余列可以分别代替半数组中的任何列，而不考虑缺陷列与哪个位的关系。保险丝存储有缺陷列的地址信息，当外部接收的列地址与存储的故障列地址之间的匹配被找到时，包含该缺陷列的位位置的读出放大器被禁止，并且输出冗余列（由哪个字线被激活选择）被复用到IO总线中。因此，在行地址信号甚至被解码之前，有缺陷的列已经被禁用，并且冗余列之一被有效地替代。该配置意味着对于每个位位置不需要具有一个冗余列，但是每个冗余列可以替代任何位位置中的有缺陷的列，并且可以替换单个位位置中的多于一个的有缺陷的列。

4. 发明授权

US4723228A Memory decoding circuit 失效
标题翻译：存储器解码电路
公开(公告)号：US4723228A
公开(公告)日：1988-02-02
申请号：US528205
申请日：1983-08-31
申请人： Ashwin H. Shah , James D. Gallia , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , James D. Gallia , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/413 , G11C7/10 , G11C8/12 , G11C11/34 , G11C11/41 , G11C11/419 , G11C8/00
CPC分类号： G11C7/10 , G11C8/12
摘要： Column decoding is performed using multiply decoded subsets of column address bits bussed across the array to multiple first stage and second stage column multiplexers. That is, for example, in an 8k by 9 memory wherein each subarray contains 16 selectable columns at each bit position, two of the address bits would be fully decoded to provide four buss lines across the chip. Each column has a primary sense amplifier, controlled by one of these four decoded lines. The outputs of each set of four primary sense amplifiers are multiplexed into a secondary sense amplifier, (preferably on a local three-scale buss) and the output of each secondary sense amplifier is selected or deselected by four buss lines which are the decoded signals corresponding to the other two address bits which select one of 16 columns. Preferably multiplexing of the output of the secondary sense amplifiers is accomplished by a three-state buffer, so that the output of these buffers can be accomplished as a wired-or function.
摘要翻译：列解码使用跨阵列总线的列地址位的多位解码子集执行到多个第一级和第二级列复用器。也就是说，例如，在8k×9存储器中，每个子阵列在每个位位置包含16个可选列，地址位中的两个将被完全解码以在芯片上提供四条总线。每列具有由这四条解码线中的一条控制的初级读出放大器。每组四个主感测放大器的输出被复用到次级读出放大器（优选地在局部三级总线上），并且每个次级读出放大器的输出由对应的解码信号的四条母线选择或取消选择到另外两个选择16列之一的地址位。优选地，二次感测放大器的输出的多路复用由三态缓冲器实现，使得这些缓冲器的输出可以被实现为有线或功能。

5. 发明授权

US4830978A Dram cell and method 失效
标题翻译：戏剧细胞和方法
公开(公告)号：US4830978A
公开(公告)日：1989-05-16
申请号：US26356
申请日：1987-03-16
申请人： Clarence W. Teng , Robert R. Doering , Ashwin H. Shah
发明人： Clarence W. Teng , Robert R. Doering , Ashwin H. Shah
IPC分类号： H01L27/10 , H01L21/225 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2254 , H01L27/10841
摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.

6. 发明授权

US4810906A Vertical inverter circuit 失效
标题翻译：垂直逆变电路
公开(公告)号：US4810906A
公开(公告)日：1989-03-07
申请号：US186724
申请日：1988-04-22
申请人： Ashwin H. Shah , Pallab K. Chatterjee
发明人： Ashwin H. Shah , Pallab K. Chatterjee
IPC分类号： H01L27/092 , H01L29/49 , H01L29/78 , H03K19/017 , H01L27/02 , H03K19/094
CPC分类号： H01L29/7827 , H01L27/092 , H01L29/495
摘要： One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.
摘要翻译：本发明的一个实施例包括一个垂直反相器。在N +型衬底的表面上形成一层P型材料，然后形成N +层，P +层，N层和P +层。（当然可以使用不同的掺杂构型并且保持在本发明的范围内。）然后沿着如此形成的层的一侧蚀刻沟槽，并且将连接器形成到中间P +和N-层。然后形成栅极绝缘体和栅极的另一个沟槽。栅极用作由此形成的N沟道晶体管和P沟道晶体管的栅极。

7. 发明授权

US5102817A Vertical DRAM cell and method 失效
标题翻译：垂直DRAM单元及方法
公开(公告)号：US5102817A
公开(公告)日：1992-04-07
申请号：US618011
申请日：1990-11-26
申请人： Pallab K. Chatterjee , Ashwin H. Shah
发明人： Pallab K. Chatterjee , Ashwin H. Shah
IPC分类号： H01L27/108
CPC分类号： H01L27/10841
摘要： DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.
摘要翻译：公开了半导体衬底上的DRAM单元和单元阵列以及制造方法，其中通过在沟槽或两个沟槽中挖掘沟槽或两个沟槽来将单元成对或成对地形成单元，以将原始单元分成两个或四个单元制造。单元包括沿着支脚侧壁的垂直场效应晶体管和电容器，其中字线和位线穿过单元。

8. 发明授权

US4673962A Vertical DRAM cell and method 失效
标题翻译：垂直DRAM单元及方法
公开(公告)号：US4673962A
公开(公告)日：1987-06-16
申请号：US714589
申请日：1985-03-21
申请人： Pallab K. Chatterjee , Ashwin H. Shah
发明人： Pallab K. Chatterjee , Ashwin H. Shah
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/06
CPC分类号： H01L27/10841 , Y10S257/911
摘要： DRAM cells and arrays of cells on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trench sidewalls with word lines and bit lines crossing over the cells.
摘要翻译：公开了半导体衬底上的DRAM单元和单元阵列以及制造方法，其中通过在沟槽或两个沟槽中挖掘出沟槽或两个沟槽来成对地或成对地形成单元，以将原始单元分成两个或四个单元制造。单元包括沿着沟槽侧壁的垂直场效应晶体管和电容器，其中字线和位线跨过单元。

9. 发明授权

US4916524A Dram cell and method 失效
标题翻译：戏剧细胞和方法
公开(公告)号：US4916524A
公开(公告)日：1990-04-10
申请号：US300467
申请日：1989-01-23
申请人： Clarence W. Teng , Robert R. Doering , Ashwin H. Shah
发明人： Clarence W. Teng , Robert R. Doering , Ashwin H. Shah
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2254 , H01L27/10841
摘要： The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench. Conductive material is then formed inside the open portion of the upper portion of the trench thereby forming a transistor connecting the upper plate of the storage capacitor to a drain region on the surface of the semiconductor substrate.
摘要翻译：本发明的所描述的实施例提供了包括形成在单个沟槽内的存储单元的结构和制造这些结构的方法。在半导体衬底的表面形成沟槽。沟槽的底部填充有多晶硅以形成存储电容器的一个板。该基板用作电容器的另一个板。然后用绝缘材料如二氧化硅填充沟槽的剩余部分。然后当将侧壁的一部分和沟槽的顶部部分向下切割到多晶电容器板时，将图案蚀刻到二氧化硅中。然后在多晶电容器板和衬底之间形成接触。掺杂原子通过接触扩散以在沟槽的侧壁上形成源区。通过氧化形成栅极绝缘体，并且在与沟槽的口相邻的沟槽的表面处形成漏极。然后，在沟槽上部的开口部分形成导电材料，从而形成将存储电容器的上板连接到半导体衬底的表面上的漏极区域的晶体管。

10. 发明授权

US4800525A Dual ended folded bit line arrangement and addressing scheme 失效
标题翻译：双端折叠位线布置和寻址方案
公开(公告)号：US4800525A
公开(公告)日：1989-01-24
申请号：US83911
申请日：1987-08-06
申请人： Ashwin H. Shah , Richard H. Womack , Chu-Ping Wang
发明人： Ashwin H. Shah , Richard H. Womack , Chu-Ping Wang
IPC分类号： G11C11/4097 , G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4097
摘要： A scheme for addressing memory cells in random access memory arrays includes bit lines divided into a plurality of segments. Each pair of bit lines has a sense amp at each end coupled to both bit lines in the pair. Word lines address memory cells coupled to each bit line of the pair. When a pair of memory cells is accessed, the bit lines are electrically divided so that one memory cell is coupled to one sense amp through one bit line, and the other memory cell is coupled to the other sense amp through the other bit line. The memory cells can be coupled to the bit lines through segment lines, with each segment line connecting a subset of the memory cells to a bit line, in order to reduce capacitances presented to the sense amps. An alternating linear array of sense amps and bit line pairs can be used to increase overall density of the memory array by allowing sense amps to access more than one bit line pair. The bit lines are addressed so that each sense amp receives data from one one bit line pair at a time. Segment lines having no currently addressed memory cells can be coupled to the sense amps in order to better balance input capacitances presented thereto. Selecting the bit line sections, segments, and memory cells in the proper order minimizes the effect of noise due to stray capacitances by causing them to appear as a common mode signal across the bit line pairs.
摘要翻译：用于寻址随机存取存储器阵列中的存储单元的方案包括分成多个段的位线。每对位线在每一端具有耦合到该对中的两个位线的感测放大器。字线寻址耦合到该对的每个位线的存储器单元。当访问一对存储器单元时，位线被电分割，使得一个存储单元通过一个位线耦合到一个读出放大器，而另一个存储单元通过另一个位线耦合到另一个读出放大器。存储器单元可以通过分段线耦合到位线，每个分段线将存储器单元的子集连接到位线，以便减小呈现给感测放大器的电容。传感放大器和位线对的交替线性阵列可以用于通过允许感测放大器访问多于一个位线对来增加存储器阵列的总体密度。位线被寻址，使得每个读出放大器一次从一个位线对接收数据。没有当前寻址的存储器单元的段线可以耦合到感测放大器，以便更好地平衡提供给它的输入电容。以适当的顺序选择位线部分，段和存储单元通过使它们在位线对上显示为共模信号来最小化由于杂散电容引起的噪声的影响。

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