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1. 发明授权

US5166765A Insulated gate field-effect transistor with pulse-shaped doping 失效
标题翻译：具有脉冲形掺杂的绝缘栅场效应晶体管
公开(公告)号：US5166765A
公开(公告)日：1992-11-24
申请号：US749772
申请日：1991-08-26
申请人： Kwing F. Lee , Abbas Ourmazd , Ran-Hong Yan
发明人： Kwing F. Lee , Abbas Ourmazd , Ran-Hong Yan
IPC分类号： H01L29/78 , H01L29/10 , H01L29/36
CPC分类号： H01L29/36 , H01L29/105 , H01L29/1083
摘要： A silicon MOSFET is provided, which can be made with an effective channel length of under one micrometer without incurring severe short-channel effects. The MOSFET includes first and second channel regions located between the source and drain regions, the first channel region overlaying the second channel region. The second channel region has a higher carrier density than the first channel region, and functions as a buried ground plane.

2. 发明授权

US5330925A Method for making a MOS device 失效
标题翻译：制造MOS器件的方法
公开(公告)号：US5330925A
公开(公告)日：1994-07-19
申请号：US900625
申请日：1992-06-18
申请人： Kwing F. Lee , Ran-Hong Yan
发明人： Kwing F. Lee , Ran-Hong Yan
IPC分类号： H01L21/336 , H01L29/08 , H01L29/78 , H01L21/265
CPC分类号： H01L29/6659 , H01L29/0847 , H01L29/66545
摘要： A method for manufacturing an MOS device, such as a PMOS transistor, on a silicon wafer. The method includes steps leading to the formation of a polysilicon gate electrode, and at least one ion-implantation step for forming source and drain junction regions in the silicon wafer. The method further comprises, before the ion-implantation step, the step of forming a first sidewall contactingly disposed adjacent the polysilicon gate electrode. The ion-implantation step is then performed such that the resulting source and drain junction regions are at least partially excluded from that portion of the silicon wafer that directly underlies the polysilicon gate electrode and the sidewall. In preferred embodiments of the invention, a first ion-implantation step is performed after the first sidewall is formed, then a second sidewall is formed adjacent and contiguous with the first sidewall, and then a second ion-implantation step is performed, resulting in the formation of further source and drain junction regions which are at least partially excluded from that portion of the silicon wafer that directly underlies the polysilicon gate electrode and the first and second sidewalls.
摘要翻译：一种用于在硅晶片上制造诸如PMOS晶体管的MOS器件的方法。该方法包括导致形成多晶硅栅电极的步骤，以及用于在硅晶片中形成源极和漏极结区域的至少一个离子注入步骤。该方法还包括在离子注入步骤之前形成邻近多晶硅栅电极接触地设置的第一侧壁的步骤。然后执行离子注入步骤，使得所得到的源极和漏极结区域至少部分地从直接位于多晶硅栅电极和侧壁下方的硅晶片部分排除。在本发明的优选实施例中，在形成第一侧壁之后进行第一离子注入步骤，然后形成与第一侧壁相邻并邻接的第二侧壁，然后执行第二离子注入步骤，形成至少部分地从硅晶片的直接位于多晶硅栅极电极和第一和第二侧壁下方的部分排除的源极和漏极结区域。

3. 发明授权

US4824796A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4824796A
公开(公告)日：1989-04-25
申请号：US77953
申请日：1987-07-10
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

4. 发明授权

US4784971A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4784971A
公开(公告)日：1988-11-15
申请号：US47946
申请日：1987-05-08
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald. C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voschenkov
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald. C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voschenkov
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

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