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1. 发明授权

US4784971A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4784971A
公开(公告)日：1988-11-15
申请号：US47946
申请日：1987-05-08
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald. C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voschenkov
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald. C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voschenkov
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

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