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1. 发明授权

US4824796A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4824796A
公开(公告)日：1989-04-25
申请号：US77953
申请日：1987-07-10
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voshchenkov , Avinoam Kornblit , Joseph Lebowitz , William T. Lynch
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

2. 发明授权

US4784971A Process for manufacturing semiconductor BICMOS device 失效
标题翻译：制造半导体BICMOS器件的工艺
公开(公告)号：US4784971A
公开(公告)日：1988-11-15
申请号：US47946
申请日：1987-05-08
申请人： Tzu-Yin Chiu , Gen M. Chin , Ronald. C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voschenkov
发明人： Tzu-Yin Chiu , Gen M. Chin , Ronald. C. Hanson , Maureen Y. Lau , Kwing F. Lee , Mark D. Morris , Alexander M. Voschenkov
IPC分类号： H01L29/73 , H01L21/225 , H01L21/3215 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L29/732 , H01L21/70 , H01L27/00
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar device during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。与外延层接触的多晶硅沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

3. 发明授权

US4992848A Self-aligned contact technology 失效
标题翻译：自对准接触技术
公开(公告)号：US4992848A
公开(公告)日：1991-02-12
申请号：US482444
申请日：1990-02-20
申请人： Gen M. Chin , Tzu-Yin Chiu , Te-Yin M. Liu , Alexander M. Voshchenkov
发明人： Gen M. Chin , Tzu-Yin Chiu , Te-Yin M. Liu , Alexander M. Voshchenkov
IPC分类号： H01L29/73 , H01L21/225 , H01L21/28 , H01L21/285 , H01L21/331 , H01L23/482
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/28 , H01L21/28525 , H01L23/4824 , H01L2924/0002
摘要： A new self-aligned contact technology is afforded by semiconductor devices having a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is afforded by interposing an insulating region therebetween. Furthermore, with a single common electrode contacting the second semiconductor regions, it is possible, among other things, to effectively reduce the parasitic capacitances of the semiconductor device as well as achieve dimensional scaling since ohmic contact to the conductive region can be made outside the fingers where physical dimensions are of no limitation.

4. 发明授权

US5106783A Process for fabricating semiconductor devices with self-aligned contacts 失效
标题翻译：用于制造具有自对准触点的半导体器件的工艺
公开(公告)号：US5106783A
公开(公告)日：1992-04-21
申请号：US611623
申请日：1990-11-09
申请人： Gen M. Chin , Tzu-Yin Chiu , Te-Yin M. Liu , Alexander M. Voshchenkov
发明人： Gen M. Chin , Tzu-Yin Chiu , Te-Yin M. Liu , Alexander M. Voshchenkov
IPC分类号： H01L21/225 , H01L21/28 , H01L21/285 , H01L21/331 , H01L23/482
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/28 , H01L21/28525 , H01L23/4824 , H01L2924/0002 , Y10S148/011
摘要： A novel process is disclosed for fabricating semiconductor devices with self-aligned contacts. Characteristic of the resulting structure is a digitated electrode and a contiguous conductive region that contact first semiconductor regions and second semiconductor regions, respectively. The first semiconductor regions and the second semiconductor regions are formed in a semiconductor substrate, with each second semiconductor region underlying a finger of the digitated electrode. Advantageously, by forming a contiguous conductive region over the first semiconductor regions located between the fingers of the digitated electrode, it is not only possible to contact second semiconductor regions with a common electrode, but also to self-align the common electrode with the digitated electrode. Ohmic shorting between the digitated electrode and the contiguous conductive region is prevented by interposing an insulating region therebetween. Furthermore, with a single common electrode contacting the second semiconductor regions, it is possible, among other things, to effectively reduce the parasitic capacitances of the semiconductor device as well as achieve dimensional scaling since ohmic contact to the conductive region can be made outside the fingers where physical dimensions are of no limitation.
摘要翻译：公开了一种用于制造具有自对准触点的半导体器件的新颖工艺。所得结构的特征是分别接触第一半导体区域和第二半导体区域的数字电极和连续的导电区域。第一半导体区域和第二半导体区域形成在半导体衬底中，其中每个第二半导体区域位于数字化电极的手指下方。有利地，通过在位于数字化电极的指状物之间的第一半导体区域上方形成邻接的导电区域，不仅可以使用公共电极接触第二半导体区域，而且可以使公共电极与数字化电极。通过在它们之间插入绝缘区域来防止数字化电极和相邻导电区域之间的欧姆短路。此外，通过与第二半导体区域接触的单个公共电极，除其他之外，有可能有效地减小半导体器件的寄生电容，并且实现尺寸缩放，因为可以在手指之外进行与导电区域的欧姆接触其中物理尺寸没有限制。

5. 发明授权

US4980304A Process for fabricating a bipolar transistor with a self-aligned contact 失效
标题翻译：用于制造具有自对准接触的双极晶体管的工艺
公开(公告)号：US4980304A
公开(公告)日：1990-12-25
申请号：US482437
申请日：1990-02-20
申请人： Gen M. Chin , Tzu-Yin Chiu , Te-Yin M. Liu , Alexander M. Voshchenkov
发明人： Gen M. Chin , Tzu-Yin Chiu , Te-Yin M. Liu , Alexander M. Voshchenkov
IPC分类号： H01L29/73 , H01L21/225 , H01L21/28 , H01L21/285 , H01L21/331 , H01L21/60 , H01L29/732
CPC分类号： H01L21/76897 , H01L21/28 , H01L21/28525 , H01L29/66272 , Y10S148/011
摘要： A novel fabrication method is disclosed for fabricating a bipolar transistor having a digitated emitter electrode and a contiguous polysilicon region acting as a self-aligned base contact. The process substantially reduces the parasitic capacitances as well as eliminates the need for the intrinsic base region to be exposed to multiple etching, which results in the fabrication of small and reproducible base widths.A first polysilicon layer is deposited over the surface of a semiconductor substrate and, then, implanted with base dopants, which are driven into the surface of the active region by a furnace process for forming an intrinsic base region. Emitter dopants are next implanted into the first polysilicon layer. Subsequently, a nitride layer is deposited and the digitated emitter fingers patterned by selective etching. Link-up regions for connecting the intrinsic base region and the extrinsic base regions to be formed later is formed by implanting portions of the substrate free of the emitter fingers with base dopants. Next, oxide sidewalls are formed on the edges of the emitter fingers by depositing a conformal oxide layer and anisotropically etching the oxide layer, leaving vertical portions thereof on the edges of each emitter finger. Finally, a second polysilicon layer is deposited conformally over the entire structure and anisotropically etched back in order to form a planar, contiguous region between each finger of the digitated electrode. Implanting the entire structure with base dopants forms the extrinsic base regions outside the fingers of the digitated electrode. Heating the substrate to cause base dopants from the first polysilicon layer to diffuse into the substrate creates emitter regions under the fingers of the digitated electrode.

6. 发明授权

US09263548B2 Method for manufacturing semiconductor devices using self-aligned process to increase device packing density 有权
公开(公告)号：US09263548B2
公开(公告)日：2016-02-16
申请号：US14595212
申请日：2015-01-13
申请人： Tzu-Yin Chiu
发明人： Tzu-Yin Chiu
IPC分类号： H01L29/66 , H01L21/768 , H01L29/78
CPC分类号： H01L29/665 , H01L21/76838 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L29/78
摘要： A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.

7. 发明申请

US20150194500A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES USING SELF-ALIGNED PROCESS TO INCREASE DEVICE PACKING DENSITY 审中-公开
标题翻译：使用自对准工艺制造半导体器件以增加器件封装密度的方法
公开(公告)号：US20150194500A1
公开(公告)日：2015-07-09
申请号：US14595212
申请日：2015-01-13
申请人： Tzu-Yin Chiu
发明人： Tzu-Yin Chiu
IPC分类号： H01L29/66
CPC分类号： H01L29/665 , H01L21/76838 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L29/78
摘要： A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.
摘要翻译：一种制造具有自对准结构的半导体集成电路的方法，所述方法包括以下步骤：提供半导体衬底; 在所述半导体衬底的顶部上形成栅极电介质层，第一多晶硅层和第一覆盖层; 图案化第一覆盖层，第一多晶硅层并停止在栅极电介质层上以形成栅极结构; 形成和图案化复合介电层，第二多晶硅层和第二覆盖层以形成互连结构; 形成复合间隔物; 去除光致抗蚀剂层; 形成第三多晶硅层; 淘汰第三多晶硅层以留下第三个多晶硅层; 去除所述第一和第二盖层; 形成源和漏极; 以及形成覆盖栅极结构，源极，漏极和互连结构的硅化物层以形成自对准结构。

8. 发明申请

US20200243206A1 Nuclides Bombardment Method and System for Neutron Generation 审中-公开
公开(公告)号：US20200243206A1
公开(公告)日：2020-07-30
申请号：US16775229
申请日：2020-01-28
申请人： Tzu-Yin Chiu
发明人： Tzu-Yin Chiu
IPC分类号： G21B1/19 , G21B1/15
摘要： A method for nuclide bombardment for neutron generation includes providing a nuclide bombardment target. The target has a metallic single-crystalline layer including a metallic element, the single-crystalline layer including lattice channels disposed of therein, and isotopes of a first element, configured as interstitial elements in the lattice channels in the single-crystalline layer. The method also includes positioning the metallic single-crystalline layer with respect to a bombardment apparatus, such that the bombardment apparatus is configured for injecting particles into the metallic single-crystalline layer substantially along the lattice channels of the single crystalline lattice. The method further includes injecting isotopes of a second element into the metallic single-crystalline layer substantially along the direction of the lattice channels, thereby increasing neutron generation.

9. 发明授权

US08828854B2 Method of impurity introduction and controlled surface removal 有权
标题翻译：杂质引入和控制表面去除方法
公开(公告)号：US08828854B2
公开(公告)日：2014-09-09
申请号：US13774092
申请日：2013-02-22
申请人： Tzu-Yin Chiu
发明人： Tzu-Yin Chiu
IPC分类号： C23C12/00 , H01L21/223 , H01L21/265 , H01L21/3065
CPC分类号： H01L21/265 , H01L21/2236 , H01L21/3065
摘要： A method of introducing dopants into a semiconductor wafer includes implanting the dopants into a region below a surface of the semiconductor wafer using an ion beam to form a first implanted layer. The dopants when activated causing a conductivity of the implanted layer to be either of N-type or P-type. The first implanted layer is characterized by a peak dopant concentration at a first depth below the surface of the semiconductor wafer. The method also includes removing a layer from the semiconductor wafer surface, wherein said layer includes a portion of said dopants.
摘要翻译：将掺杂剂引入半导体晶片的方法包括使用离子束将掺杂剂注入到半导体晶片的表面下方的区域中以形成第一注入层。激活时的掺杂剂使注入层的导电性为N型或P型。第一注入层的特征在于在半导体晶片的表面下方的第一深度处的峰值掺杂剂浓度。该方法还包括从半导体晶片表面去除层，其中所述层包括一部分所述掺杂剂。

10. 发明授权

US5470783A Method for integrated circuit device isolation 失效
标题翻译：集成电路器件隔离方法
公开(公告)号：US5470783A
公开(公告)日：1995-11-28
申请号：US369977
申请日：1995-01-09
申请人： Tzu-Yin Chiu , Frank M. Erceg , Te-Yin M. Liu , Kenenth G. Moerschel , Michael A. Prozonic , Janmye Sung
发明人： Tzu-Yin Chiu , Frank M. Erceg , Te-Yin M. Liu , Kenenth G. Moerschel , Michael A. Prozonic , Janmye Sung
IPC分类号： H01L21/316 , H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76205 , H01L21/32 , Y10S148/05
摘要： An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls. The exposed portions of the second nitride layer are then removed, leaving only those portions of the second nitride layer that are interposed between the polycrystalline material and the sidewalls on the substrate surface. The remaining portions of the polycrystalline material on the surface of the structure are then removed. The field oxide is then grown on the field oxide region of the substrate. The portions of the second nitride layer on the sidewalls are lifted and bent as the oxide is grown. The lifting and bending of the second nitride layer forms grooves in the field oxide as it is grown. The remaining layers of the mask are then removed. A thin layer of oxide is then grown or deposited on the surface of the substrate. A layer of nitride with a thickness that is at least one-half the width of the grooves in the field oxide is deposited on the substrate surface. The nitride layer is then removed except for that portion of the nitride in the grooves.
摘要翻译：公开了一种用于在衬底中产生场氧化物区域的集成电路制造工艺。在该过程中，在衬底上形成氧化物，氮化物和沉积的二氧化硅的掩蔽层。通过这些掩模层将限定衬底中的场氧化物区域的图案引入到衬底中。场氧化物区域由衬底的一部分中的陡峭的侧壁和覆盖衬底的掩模层所界定。在衬底的暴露部分上生长薄层的氧化物，并且在衬底/掩模结构之上形成保形第二氮化层，随后是多晶材料的共形层。选择性地去除多晶层，使得保留在结构上的多晶材料的唯一部分是覆盖侧壁的部分。然后去除第二氮化物层的暴露部分，仅留下介于多晶材料和衬底表面上的侧壁之间的第二氮化物层的那些部分。然后除去结构表面上的多晶材料的剩余部分。然后，场氧化物在衬底的场氧化物区域上生长。当氧化物生长时，侧壁上的第二氮化物层的部分被提升和弯曲。当第二氮化物层生长时，第二氮化物层的提升和弯曲在场氧化物中形成凹槽。然后去除掩模的剩余层。然后在衬底的表面上生长或沉积薄层氧化物。厚度为场氧化物中沟槽宽度的至少一半的氮化物层沉积在衬底表面上。然后去除氮化物层，除了沟槽中的那部分氮化物。

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