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1. 发明授权

US08120973B2 Write driver of semiconductor memory device 有权
标题翻译：写半导体存储器件的驱动器
公开(公告)号：US08120973B2
公开(公告)日：2012-02-21
申请号：US12487181
申请日：2009-06-18
申请人： Mun-Phil Park , Kwi-Dong Kim , Sung-Ho Kim
发明人： Mun-Phil Park , Kwi-Dong Kim , Sung-Ho Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1096 , G11C8/08
摘要： A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals.
摘要翻译：半导体存储器件包括第一存储器组和第二存储器组以及公共写入驱动器，其被配置为将写入数据驱动到第一存储器组和第二存储器组的激活存储器组。半导体存储器件的公共写入驱动器包括：公共写入控制块，被配置为产生与写入数据相对应的公共驱动控制信号，以及公共写入驱动块，被配置为驱动第一存储体的传输线或第二存储器的传输线存储体，其响应于公共驱动控制信号由存储体选择信号选择。

2. 发明申请

US20110103163A1 MULTI-BIT TEST CONTROL CIRCUIT 有权
标题翻译：多位测试控制电路
公开(公告)号：US20110103163A1
公开(公告)日：2011-05-05
申请号：US12792444
申请日：2010-06-02
申请人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
发明人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.
摘要翻译：多位测试控制电路包括操作单元，延迟单元和生成单元。操作单元被配置为将输入到每个存储体的单个源信号与通过将源信号延迟一定时间而产生的延迟信号组合以产生第一脉冲信号。延迟单元被配置为将第一脉冲信号延迟一定时间。生成单元被配置为将操作单元的输出信号与延迟单元的输出信号组合，以产生用于存储体交叉多位测试的第二脉冲信号。

3. 发明申请

US20100246296A1 Write Driver and Semiconductor Memory Device Using the Same 有权
标题翻译：使用相同的驱动器和半导体存储器件
公开(公告)号：US20100246296A1
公开(公告)日：2010-09-30
申请号：US12487181
申请日：2009-06-18
申请人： Mun-Phil Park , Kwi-Dong Kim , Sung-Ho Kim
发明人： Mun-Phil Park , Kwi-Dong Kim , Sung-Ho Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1096 , G11C8/08
摘要： A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals.
摘要翻译：半导体存储器件包括第一存储器组和第二存储器组以及公共写入驱动器，其被配置为将写入数据驱动到第一存储器组和第二存储器组的激活存储器组。半导体存储器件的公共写入驱动器包括：公共写入控制块，被配置为产生与写入数据相对应的公共驱动控制信号;以及公共写入驱动块，被配置为驱动第一存储体的传输线或第二存储器的传输线存储体，其响应于公共驱动控制信号由存储体选择信号选择。

4. 发明授权

US08379473B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08379473B2
公开(公告)日：2013-02-19
申请号：US12614867
申请日：2009-11-09
申请人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
发明人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/10 , G11C8/18 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.
摘要翻译：半导体存储器件包括分别响应于第一和第二存储体选通信号而对第一和第二存储体执行数据写入操作的第一和第二写入驱动块，以及用于将数据传输到第一和第二写入的公共输入驱动块驱动块通过公共数据线响应于第一和第二存储体的访问信息。

5. 发明授权

US08233338B2 Multi-bit test control circuit 有权
标题翻译：多位测试控制电路
公开(公告)号：US08233338B2
公开(公告)日：2012-07-31
申请号：US12792444
申请日：2010-06-02
申请人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
发明人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.
摘要翻译：多位测试控制电路包括操作单元，延迟单元和生成单元。操作单元被配置为将输入到每个存储体的单个源信号与通过将源信号延迟一定时间而产生的延迟信号组合以产生第一脉冲信号。延迟单元被配置为将第一脉冲信号延迟一定时间。生成单元被配置为将操作单元的输出信号与延迟单元的输出信号组合，以产生用于存储体交叉多位测试的第二脉冲信号。

6. 发明申请

US20110002179A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20110002179A1
公开(公告)日：2011-01-06
申请号：US12614867
申请日：2009-11-09
申请人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
发明人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/10 , G11C8/18 , G11C11/4076 , G11C11/4096
摘要： A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.
摘要翻译：半导体存储器件包括分别响应于第一和第二存储体选通信号而对第一和第二存储体执行数据写入操作的第一和第二写入驱动块，以及用于将数据传输到第一和第二写入的公共输入驱动块驱动块通过公共数据线响应于第一和第二存储体的访问信息。

7. 发明授权

US08050136B2 Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same 有权
标题翻译：半导体存储器件，用于保证数据传输的可靠性和包括其的半导体系统
公开(公告)号：US08050136B2
公开(公告)日：2011-11-01
申请号：US12494669
申请日：2009-06-30
申请人： Mun-Phil Park
发明人： Mun-Phil Park
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/222
摘要： A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
摘要翻译：半导体器件包括：系统时钟输入单元，被配置为接收用于同步地址信号的输入时间和来自存储器控制器的命令信号的系统时钟;数据时钟输入单元，被配置为接收第一和第二数据时钟，用于使输入/ 来自存储器控制器的数据信号的输出时间，其中根据训练信息信号偏移第二数据时钟的相位，并且具有移位相位的第二数据时钟被输入到数据时钟输入单元，并且相位检测单元，被配置为基于第一数据时钟的边缘来检测第二数据时钟的逻辑电平，并且生成训练信息信号，以根据检测到的逻辑电平将生成的信号发送到存储器控制器。

8. 发明授权

US07843755B2 Circuit and method for controlling sense amplifier of semiconductor memory apparatus 有权
标题翻译：用于控制半导体存储器件读出放大器的电路和方法
公开(公告)号：US07843755B2
公开(公告)日：2010-11-30
申请号：US12363947
申请日：2009-02-02
申请人： Mun-Phil Park
发明人： Mun-Phil Park
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C8/08 , G11C7/02 , G11C7/08 , G11C7/12 , G11C11/406 , G11C11/4091 , G11C11/4094 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C2029/1202 , G11C2211/4065
摘要： A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.
摘要翻译：一种用于控制半导体存储装置的读出放大器的电路，包括：读出放大器控制单元，根据刷新信号是否有效，控制由有效命令和预充电命令产生的读出放大器控制信号的使能点。读出放大器驱动器，其响应于读出放大器控制信号的输入和位线均衡信号产生读出放大器驱动信号。

9. 发明授权

US08305838B2 Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same 有权
标题翻译：半导体存储器件，用于保证数据传输的可靠性和包括其的半导体系统
公开(公告)号：US08305838B2
公开(公告)日：2012-11-06
申请号：US13243697
申请日：2011-09-23
申请人： Mun-Phil Park
发明人： Mun-Phil Park
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/222
摘要： A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
摘要翻译：半导体器件包括：系统时钟输入单元，被配置为接收用于同步地址信号的输入时间和来自存储器控制器的命令信号的系统时钟;数据时钟输入单元，被配置为接收第一和第二数据时钟，用于使输入/ 来自存储器控制器的数据信号的输出时间，其中根据训练信息信号偏移第二数据时钟的相位，并且具有移位相位的第二数据时钟被输入到数据时钟输入单元，并且相位检测单元，被配置为基于第一数据时钟的边缘来检测第二数据时钟的逻辑电平，并且生成训练信息信号，以根据检测到的逻辑电平将生成的信号发送到存储器控制器。

10. 发明申请

US20070247942A1 Circuit and method for controlling sense amplifier of semiconductor memory apparatus 失效
标题翻译：用于控制半导体存储器件读出放大器的电路和方法
公开(公告)号：US20070247942A1
公开(公告)日：2007-10-25
申请号：US11637756
申请日：2006-12-13
申请人： Mun-Phil Park
发明人： Mun-Phil Park
IPC分类号： G11C7/02 , G11C7/00 , G11C8/00
CPC分类号： G11C8/08 , G11C7/02 , G11C7/08 , G11C7/12 , G11C11/406 , G11C11/4091 , G11C11/4094 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C2029/1202 , G11C2211/4065
摘要： A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.
摘要翻译：一种用于控制半导体存储装置的读出放大器的电路，包括：读出放大器控制单元，根据刷新信号是否有效，控制由有效命令和预充电命令产生的读出放大器控制信号的使能点。读出放大器驱动器，其响应于读出放大器控制信号的输入和位线均衡信号产生读出放大器驱动信号。

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