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    • 1. 发明授权
    • Write driver of semiconductor memory device
    • 写半导体存储器件的驱动器
    • US08120973B2
    • 2012-02-21
    • US12487181
    • 2009-06-18
    • Mun-Phil ParkKwi-Dong KimSung-Ho Kim
    • Mun-Phil ParkKwi-Dong KimSung-Ho Kim
    • G11C7/00
    • G11C7/1078G11C7/1096G11C8/08
    • A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals.
    • 半导体存储器件包括第一存储器组和第二存储器组以及公共写入驱动器,其被配置为将写入数据驱动到第一存储器组和第二存储器组的激活存储器组。 半导体存储器件的公共写入驱动器包括:公共写入控制块,被配置为产生与写入数据相对应的公共驱动控制信号,以及公共写入驱动块,被配置为驱动第一存储体的传输线或第二存储器的传输线 存储体,其响应于公共驱动控制信号由存储体选择信号选择。
    • 7. 发明授权
    • Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same
    • 半导体存储器件,用于保证数据传输的可靠性和包括其的半导体系统
    • US08050136B2
    • 2011-11-01
    • US12494669
    • 2009-06-30
    • Mun-Phil Park
    • Mun-Phil Park
    • G11C8/00
    • G11C7/22G06F13/1689G11C7/222
    • A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
    • 半导体器件包括:系统时钟输入单元,被配置为接收用于同步地址信号的输入时间和来自存储器控制器的命令信号的系统时钟;数据时钟输入单元,被配置为接收第一和第二数据时钟,用于使输入/ 来自存储器控制器的数据信号的输出时间,其中根据训练信息信号偏移第二数据时钟的相位,并且具有移位相位的第二数据时钟被输入到数据时钟输入单元,并且相位检测 单元,被配置为基于第一数据时钟的边缘来检测第二数据时钟的逻辑电平,并且生成训练信息信号,以根据检测到的逻辑电平将生成的信号发送到存储器控制器。
    • 9. 发明授权
    • Semiconductor memory device for guaranteeing reliability of data transmission and semiconductor system including the same
    • 半导体存储器件,用于保证数据传输的可靠性和包括其的半导体系统
    • US08305838B2
    • 2012-11-06
    • US13243697
    • 2011-09-23
    • Mun-Phil Park
    • Mun-Phil Park
    • G11C8/00
    • G11C7/22G06F13/1689G11C7/222
    • A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.
    • 半导体器件包括:系统时钟输入单元,被配置为接收用于同步地址信号的输入时间和来自存储器控制器的命令信号的系统时钟;数据时钟输入单元,被配置为接收第一和第二数据时钟,用于使输入/ 来自存储器控制器的数据信号的输出时间,其中根据训练信息信号偏移第二数据时钟的相位,并且具有移位相位的第二数据时钟被输入到数据时钟输入单元,并且相位检测 单元,被配置为基于第一数据时钟的边缘来检测第二数据时钟的逻辑电平,并且生成训练信息信号,以根据检测到的逻辑电平将生成的信号发送到存储器控制器。