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1. 发明授权

US5710711A Method and integrated circuit adapted for partial scan testability 失效
标题翻译：适用于部分扫描可测性的方法和集成电路
公开(公告)号：US5710711A
公开(公告)日：1998-01-20
申请号：US550421
申请日：1995-10-30
申请人： Kwang-Ting Cheng , Jing-Yang Jou
发明人： Kwang-Ting Cheng , Jing-Yang Jou
IPC分类号： G01R31/3185 , G06F17/50
CPC分类号： G01R31/318586
摘要： A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memory elements in a circuit based on their ability to eliminate feedback cycles in the circuit and on considerations of the potential performance degradation due to the inclusion of scan memory elements. A feedback cycle is defined as a feedback path from the output of a memory element to the input of said memory element.
摘要翻译：教导了一种修改用于部分扫描测试的数字集成电路的方法和装置，并且对电路的性能特征几乎没有或没有影响。说明性地，扫描存储器元件是基于它们消除电路中的反馈循环的能力以及由于包含扫描存储器元件而引起的潜在性能下降的考虑，从电路中的所有存储元件中选择的。反馈周期被定义为从存储元件的输出到所述存储器元件的输入的反馈路径。

2. 发明申请

US20110153709A1 DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS 审中-公开
标题翻译：延迟用于基于LUT的FPGAS的最佳压缩机树合成
公开(公告)号：US20110153709A1
公开(公告)日：2011-06-23
申请号：US12717520
申请日：2010-03-04
申请人： Juinn-Dar HUANG , Jhih-Hong Lu , Bu-Ching Lin , Jing-Yang Jou
发明人： Juinn-Dar HUANG , Jhih-Hong Lu , Bu-Ching Lin , Jing-Yang Jou
IPC分类号： G06F7/50
CPC分类号： G06F7/5318
摘要： A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture.
摘要翻译：一种称为DOCT的压缩器树合成算法，其保证了基于LUT的FPGA中的延迟最优实现。给定一个有针对性的K输入LUT架构，DOCT首先将有限的主要模式集合作为必要的构建块。然后，它表明延迟最优压缩器树可以总是通过整数线性规划（ILP）由那些导出的素数模式来构造。在不损失延迟最优性的情况下，调用后处理过程以减少所生成的压缩器树设计所需的LUT的数量。已经对广泛的基准电路进行了DOCT评估。 DOCT基于现代的基于8输入LUT的FPGA架构，降低了压缩树的深度和LUT的数量。

3. 发明授权

US06675337B1 Built-in self verification circuit for system chip design 失效
标题翻译：内置自检电路，用于系统芯片设计
公开(公告)号：US06675337B1
公开(公告)日：2004-01-06
申请号：US09630905
申请日：2000-08-02
申请人： Shing-Wu Tung , Chun-Yao Wang , Jing-Yang Jou
发明人： Shing-Wu Tung , Chun-Yao Wang , Jing-Yang Jou
IPC分类号： G01R3128
CPC分类号： G01R31/318342
摘要： A built-in verification circuit having a circuit-under-test circuit, a test pattern generator, a bi-directional signal flow switch and three unidirectional, signal flow switches. The test pattern generator produces a testing pattern based on an input/output port order fault model. The bi-directional signal flow switch is positioned between the input terminal of the built-in verification circuit and the circuit-under-test circuit. The first unidirectional signal flow switch is positioned between the circuit-under-test circuit and the test pattern generator. The second unidirectional signal flow switch is positioned between the circuit-under-test circuit and the output terminal of the built-in verification circuit. The third unidirectional signal flow switch is positioned between the test pattern generator and the output terminal of the built-in verification circuit. The bi-directional signal flow switch and the first unidirectional signal flow switch are used for controlling the input terminal of the built-in verification circuit and the signal flow direction of the test pattern generator. The second and the third unidirectional signal flow switch are used for controlling the signal source of the output from the built-in verification circuit.
摘要翻译：具有电路不足测试电路，测试图形发生器，双向信号流开关和三个单向信号流开关的内置验证电路。测试模式生成器基于输入/输出端口顺序故障模型生成测试模式。双向信号流开关位于内置验证电路的输入端和被测电路之间。第一单向信号流开关位于测试电路和测试图案发生器之间。第二单向信号流开关位于被测电路和内置验证电路的输出端之间。第三单向信号流开关位于测试图形发生器和内置验证电路的输出端之间。双向信号流开关和第一单向信号流开关用于控制内置验证电路的输入端和测试模式发生器的信号流向。第二和第三单向信号流开关用于控制来自内置验证电路的输出的信号源。

4. 发明授权

US4768196A Programmable logic array 失效
标题翻译：可编程逻辑阵列
公开(公告)号：US4768196A
公开(公告)日：1988-08-30
申请号：US923984
申请日：1986-10-28
申请人： Jing-Yang Jou , Christopher Rosebrugh
发明人： Jing-Yang Jou , Christopher Rosebrugh
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G06F11/27 , H03K19/177 , G01R31/02
CPC分类号： G01R31/318516 , G06F11/27
摘要： Built-in self-test programmable logic arrays use a deterministic test pattern generator to generate test patterns such that each cross point in an AND-plane can be evaulated sequentially. A multiple input signature register which uses X.sup.Q +1 as its characteristic polynomial is used to evaulate the test results, where Q is the number of outputs. The final signature can be further compressed into only one bit. Instead of only determining the probability of fault detection, in this scheme, the fault detection capability has been analyzed using both the stuck at fault and the contact fault model. It can be shown that all of these faults can be detected. Shorts between two adjacent lines can be detected by using NOR gates.
摘要翻译：内置自检可编程逻辑阵列使用确定性测试模式发生器来产生测试模式，使得可以依次对AND平面中的每个交叉点进行排除。使用XQ + 1作为特征多项式的多输入签名寄存器用于表示测试结果，其中Q是输出数。最后的签名可以进一步压缩成只有一个位。而不是仅仅确定故障检测的概率，在这种方案中，故障检测能力已经使用故障和接触故障模型进行了分析。可以看出可以检测到所有这些故障。可以通过使用NOR门检测两条相邻行之间的短路。

5. 发明授权

US07571414B2 Multi-project system-on-chip and its method 失效
标题翻译：多项目片上系统及其方法
公开(公告)号：US07571414B2
公开(公告)日：2009-08-04
申请号：US11453103
申请日：2006-06-15
申请人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
发明人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/66
摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.
摘要翻译：通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程从而得出。

6. 发明申请

US20070294658A1 Multi-project system-on-chip and its method 失效
标题翻译：多项目片上系统及其方法
公开(公告)号：US20070294658A1
公开(公告)日：2007-12-20
申请号：US11453103
申请日：2006-06-15
申请人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
发明人： Chun-Ming Huang , Chih-Chyau Yang , Jing-Yang Jou , Kuen-Jong Lee , Lan-Da Van
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/66
摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.
摘要翻译：通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程从而得出。

7. 发明授权

US07577780B2 Fine-grained bandwidth control arbiter and the method thereof 有权
标题翻译：细粒度带宽控制仲裁器及其方法
公开(公告)号：US07577780B2
公开(公告)日：2009-08-18
申请号：US11711663
申请日：2007-02-28
申请人： Juinn-Dar Huang , Bu-Ching Lin , Geeng-Wei Lee , Jing-Yang Jou
发明人： Juinn-Dar Huang , Bu-Ching Lin , Geeng-Wei Lee , Jing-Yang Jou
IPC分类号： G06F13/36
CPC分类号： G06F13/362
摘要： A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.
摘要翻译：一个细粒度的带宽控制仲裁器管理具有实时和/或带宽要求的主机的请求的共享总线使用情况，而且主机分别预设了一个机票。仲裁器由三个组件组成，一个实时处理程序，一个带宽调节器和一个调节权重的彩票管理器。实时处理程序提供最紧急的请求。带宽调节器处理带宽分配，并阻止满足带宽需求的主机的请求。调整权重的彩票管理人员根据车票授权随机地授予了竞争主人之一。

8. 发明申请

US20080209093A1 Fine-grained bandwidth control arbiter and the method thereof 有权
标题翻译：细粒度带宽控制仲裁器及其方法
公开(公告)号：US20080209093A1
公开(公告)日：2008-08-28
申请号：US11711663
申请日：2007-02-28
申请人： Juinn-Dar Huang , Bu-Ching Lin , Geeng-Wei Lee , Jing-Yang Jou
发明人： Juinn-Dar Huang , Bu-Ching Lin , Geeng-Wei Lee , Jing-Yang Jou
IPC分类号： G06F13/36
CPC分类号： G06F13/362
摘要： A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.
摘要翻译：一个细粒度的带宽控制仲裁器管理具有实时和/或带宽要求的主机的请求的共享总线使用情况，而且主机分别预设了一个机票。仲裁器由三个组件组成，一个实时处理程序，一个带宽调节器和一个调节权重的彩票管理器。实时处理程序提供最紧急的请求。带宽调节器处理带宽分配，并阻止满足带宽需求的主机的请求。调整权重的彩票管理人员根据车票授权随机地授予了竞争主人之一。

9. 发明授权

US07013457B2 Prioritized debugging of an error space in program code 有权
标题翻译：程序代码中错误空间的优先调试
公开(公告)号：US07013457B2
公开(公告)日：2006-03-14
申请号：US09682140
申请日：2001-07-26
申请人： Tai-Ying Chiang , Jing-Yang Jou , Ming-Chih Lai , Jien-Shen Tsai
发明人： Tai-Ying Chiang , Jing-Yang Jou , Ming-Chih Lai , Jien-Shen Tsai
IPC分类号： G06F9/44
CPC分类号： G06F11/362
摘要： A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs from a desired value. An error set of the error variable is obtained, which is a subset of the statements in the computer readable code. Each statement in the error set is relationally connected to the error variable. A priority value is given to each statement in the error set. The priority values indicate a computed probability that the associated statement is an error source of the error variable. Finally, the output system is used to present each statement in the error set in an ordered manner according to the priority values.
摘要翻译：计算机系统具有输入系统和输出系统。要调试的程序代码具有多个程序代码语句。输入系统用于指示程序代码中的错误变量。错误变量的值与所需值不同。获得错误变量的错误集，这是计算机可读代码中的语句的一个子集。错误集中的每个语句都与错误变量相关联。给出错误集中的每个语句的优先级值。优先级值表示计算出的关联语句是错误变量的错误源的概率。最后，输出系统用于根据优先级值以有序的方式向错误集中呈现每个语句。

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