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1. 发明授权

US07158970B2 Maximizing expected generalization for learning complex query concepts 失效
标题翻译：最大化学习复杂查询概念的预期泛化
公开(公告)号：US07158970B2
公开(公告)日：2007-01-02
申请号：US10116383
申请日：2002-04-02
申请人： Edward Y. Chang , Kwang-Ting Cheng
发明人： Edward Y. Chang , Kwang-Ting Cheng
IPC分类号： G06F17/30 , G06F7/00
CPC分类号： G06F17/30967 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935
摘要： A method of learning a user query concept is provided which includes a sample selection stage and a feature reduction stage; during the sample selection stage, sample objects are selected from a query concept sample space bounded by a k-CNF and a k-DNF; the selected sample objects include feature sets that are no more than a prescribed amount different from a corresponding feature set defined by the k-CNF; during the feature reduction stage, individual features are removed from the k-CNF that are identified as differing from corresponding individual features of sample objects indicated by the user to be close to the user's query concept; also during the feature reduction stage, individual features are removed from the k-DNF that are identified as not differing from corresponding individual features of sample objects indicated by the user to be not close to the user's query concept.
摘要翻译：提供了一种学习用户查询概念的方法，其包括样本选择阶段和特征缩减阶段; 在样本选择阶段，从由k-CNF和k-DNF界定的查询概念样本空间中选择样本对象; 所选择的样本对象包括不超过与k-CNF定义的相应特征集不同的规定量的特征集; 在特征缩减阶段，将各个特征从k-CNF中移除，所述k-CNF被识别为与用户指示的样本对象的相应单独特征不同以接近用户的查询概念; 还在特征缩减阶段期间，从k-DNF中移除被识别为与用户指示的不同于用户查询概念的样本对象的相应单独特征不同的各个特征。

2. 发明授权

US06694466B1 Method and system for improving the test quality for scan-based BIST using a general test application scheme 失效
标题翻译：使用一般测试应用方案提高基于扫描的BIST测试质量的方法和系统
公开(公告)号：US06694466B1
公开(公告)日：2004-02-17
申请号：US09428242
申请日：1999-10-27
申请人： Huan-Chih Tsai , Kwang-Ting Cheng , Sudipta Bhawmik
发明人： Huan-Chih Tsai , Kwang-Ting Cheng , Sudipta Bhawmik
IPC分类号： G01R3128
CPC分类号： G01R31/318544
摘要： A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.
摘要翻译：针对现有的基于扫描的BIST架构提出了一般的测试应用方案。目的是进一步提高测试质量，而不会向“被测电路”（CUT）插入附加逻辑。所提出的测试方案将整个测试过程分为多个测试阶段。在每个测试会话中测试模式扫描后应用不同数量的捕获周期，以最大限度地提高不同故障子集的故障检测。提出了一个过程，以找出每个故障每个扫描序列之后的最佳捕获周期数。基于该信息，确定每个扫描序列之后的测试次数和捕获周期数以最大化CUT的随机可测试性。

3. 发明授权

US06976016B2 Maximizing expected generalization for learning complex query concepts 失效
标题翻译：最大化学习复杂查询概念的预期泛化
公开(公告)号：US06976016B2
公开(公告)日：2005-12-13
申请号：US10032319
申请日：2001-12-21
申请人： Edward Y. Chang , Kwang-Ting Cheng
发明人： Edward Y. Chang , Kwang-Ting Cheng
IPC分类号： G06F17/30
CPC分类号： G06F17/30967 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935
摘要： A method of learning user query concept for searching visual images encoded in computer readable storage media comprising: providing a multiplicity of sample images encoded in a computer readable medium; providing a multiplicity of sample expressions that correspond to sample images and in which terms of the sample expressions represent features of corresponding sample images; defining a user query concept sample space bounded by a boundary k-CNF expression and by a boundary k-DNF expression refining the user query concept sample space by, soliciting user feedback as to which of the multiple presented sample images are close to the user's query concept; removing from the boundary k-CNF expression disjunctive terms based upon the solicited user feedback; and removing from the boundary k-DNF expression respective conjunctive terms based upon the solicited user feedback.
摘要翻译：一种用于搜索在计算机可读存储介质中编码的可视图像的用户查询概念的方法，包括：提供在计算机可读介质中编码的多个样本图像; 提供对应于样本图像的多个样本表达式，并且样本表达式的哪些项表示相应样本图像的特征; 定义由边界k-CNF表达式界定的用户查询概念样本空间，以及通过边界k-DNF表达式来提炼用户查询概念样本空间的用户查询概念样本空间，征求用户对多个呈现的样本图像中的哪一个接近用户查询的反馈概念; 根据被请求的用户反馈从边界k-CNF表达分离术语中去除; 并根据所请求的用户反馈从边界k-DNF表达中移除各自的连接项。

4. 发明授权

US06256759B1 Hybrid algorithm for test point selection for scan-based BIST 失效
标题翻译：用于基于扫描的BIST的测试点选择的混合算法
公开(公告)号：US06256759B1
公开(公告)日：2001-07-03
申请号：US09097488
申请日：1998-06-15
申请人： Sudipta Bhawmik , Kwang-Ting Cheng , Chih-Jen Lin , Huan-Chih Tsai
发明人： Sudipta Bhawmik , Kwang-Ting Cheng , Chih-Jen Lin , Huan-Chih Tsai
IPC分类号： G01R3128
CPC分类号： G01R31/318591 , G06F2217/14
摘要： A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.
摘要翻译：用于基于扫描的内置自检（BIST）的测试点选择方法。该方法计算混合成本降低（HCR）值作为被测电路中所有节点的相应实际成本降低的估计值。然后选择具有最大HCR的测试点。该迭代过程一直持续到被测电路的故障覆盖范围达到所需值或所选择的测试点数等于最大测试点数。在替代实施例中，针对被测电路中的所有节点计算成本降低因子，仅对选定的候选集合计算HCR，并且选择具有最大HCR的候选者作为测试点。测试点选择方法相对于常规选择方法实现了更高的故障覆盖结果，并减少了计算处理。

5. 发明授权

US5828828A Method for inserting test points for full-and-partial-scan built-in self-testing 失效
标题翻译：插入全部和部分扫描内置自检的测试点的方法
公开(公告)号：US5828828A
公开(公告)日：1998-10-27
申请号：US939498
申请日：1997-09-29
申请人： Chih-Jen Lin , Kwang-Ting Cheng
发明人： Chih-Jen Lin , Kwang-Ting Cheng
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318586 , G01R31/318583
摘要： Test points (20, 24) placed at selected nodes (16) within a circuit (10) based on a cost function that accounts for (a) the global improvement in testability and (b) the penalty in circuit performance associated with propagation delays attributable to such test points. By accounting for both the global impact on testability and circuit performance degradation, the cost function maximizes fault coverage while achieving nearly minimal impairment of circuit performance.
摘要翻译：基于成本函数放置在电路（10）内的选定节点（16）处的测试点（20,24），其考虑到（a）可测试性的全局改进，以及（b）与传播延迟相关的电路性能中的惩罚可归因于到这样的测试点。通过考虑全球对可测试性和电路性能下降的影响，成本函数可最大限度地提高故障覆盖范围，同时实现电路性能的几乎最小的损害。

6. 发明授权

US5587919A Apparatus and method for logic optimization by redundancy addition and removal 失效
标题翻译：通过冗余添加和删除进行逻辑优化的装置和方法
公开(公告)号：US5587919A
公开(公告)日：1996-12-24
申请号：US233791
申请日：1994-04-22
申请人： Kwang-Ting Cheng , Luis Entrena
发明人： Kwang-Ting Cheng , Luis Entrena
IPC分类号： G01R31/3183 , G06F17/50
CPC分类号： G01R31/318342 , G06F17/505
摘要： A method is disclosed for optimizing a digital logic network through the iterative addition and removal of redundant connections. Redundancy testing is performed on connections absolutely dominated by the node of the network being optimized to find redundant connections and connections that can be added to the network which would create more redundant connections elsewhere in the network which may under appropriate conditions be removed to simplify the network. Application of the redundancy addition and removal network optimization technique to selected connections in a network improves the cost efficiency of network optimization because a network is optimized by the consideration of a reduced number of candidate connections for addition.
摘要翻译：公开了一种通过迭代添加和删除冗余连接来优化数字逻辑网络的方法。对正在被网络节点绝对主导的连接进行冗余测试，该节点被优化以找到可以添加到网络中的冗余连接和连接，从而在网络中的其他地方创建更多的冗余连接，这可以在适当的条件下被去除以简化网络。冗余添加和删除网络优化技术在网络中的选择连接中的应用提高了网络优化的成本效率，因为通过考虑减少的候选连接数来优化网络。

7. 发明授权

US5513122A Method and apparatus for determining the reachable states in a hybrid model state machine 失效
标题翻译：用于确定混合模型状态机中的可达状态的方法和装置
公开(公告)号：US5513122A
公开(公告)日：1996-04-30
申请号：US254218
申请日：1994-06-06
申请人： Kwang-Ting Cheng , Anjur S. Krishnakumar
发明人： Kwang-Ting Cheng , Anjur S. Krishnakumar
IPC分类号： G06F17/50 , G05B19/045 , G06F11/26
CPC分类号： G06F17/504
摘要： The present invention provides a method and apparatus for more efficiently validating high-level specifications of sequential digital systems, and in particular, those represented by hybrid models. According to the present invention, the high-level representation of a system is converted into a direct sum EFSM. An operator or a data file then provides an initial configuration or set of initial configurations of states and variable values. The method of the present invention then determines the set of configuration reachable from the initial configuration through symbolic execution of the direct sum EFSM. By representing the transitional relations of the machine as the and-product of Boolean expressions and arithmetic expressions, each class of expressions may be processed separately. When complete, the symbolic execution produces a cover of the set of reachable states. The results may then be reviewed to determine if the given specification produces unexpected or incompatible results.
摘要翻译：本发明提供了一种用于更有效地验证连续数字系统的高级规范的方法和装置，特别是由混合模型表示的那些。根据本发明，系统的高级表示被转换为直接总和EFSM。然后，操作员或数据文件提供状态和变量值的初始配置或一组初始配置。然后，本发明的方法通过直接和EFSM的符号执行确定从初始配置可达到的配置集合。通过将机器的过渡关系表示为布尔表达式和算术表达式的乘积，可以单独处理每个类的表达式。完成后，符号执行会产生一组可达状态的覆盖。然后可以检查结果以确定给定规格是否产生意外或不兼容的结果。

8. 发明授权

US06345373B1 System and method for testing high speed VLSI devices using slower testers 有权
标题翻译：使用较慢测试仪测试高速VLSI器件的系统和方法
公开(公告)号：US06345373B1
公开(公告)日：2002-02-05
申请号：US09296267
申请日：1999-04-22
申请人： Srimat T. Chakradhar , Angela Krstic , Kwang-Ting Cheng
发明人： Srimat T. Chakradhar , Angela Krstic , Kwang-Ting Cheng
IPC分类号： G06F1100
CPC分类号： G01R31/31922 , G01R31/31707 , G01R31/31908
摘要： At-speed strategies for testing high speed designs on slower testers. At-speed testing schemes is provided that integrates the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. A slow tester that uses test vectors that are generated while taking into account the speed of the tester.
摘要翻译：用于在较慢测试仪上测试高速设计的速度策略。提供了将测试仪速度限制与测试生成过程相结合的高速测试方案。由于在测试生成过程中的限制，这些方案可能会导致故障覆盖率的降低。为了增加故障覆盖范围并减少测试应用时间，可以组合慢速慢速和速度快的策略，以测试较慢测试仪的高速设计。一个缓慢的测试器，使用测试矢量，同时考虑到测试仪的速度。

9. 发明授权

US5710711A Method and integrated circuit adapted for partial scan testability 失效
标题翻译：适用于部分扫描可测性的方法和集成电路
公开(公告)号：US5710711A
公开(公告)日：1998-01-20
申请号：US550421
申请日：1995-10-30
申请人： Kwang-Ting Cheng , Jing-Yang Jou
发明人： Kwang-Ting Cheng , Jing-Yang Jou
IPC分类号： G01R31/3185 , G06F17/50
CPC分类号： G01R31/318586
摘要： A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memory elements in a circuit based on their ability to eliminate feedback cycles in the circuit and on considerations of the potential performance degradation due to the inclusion of scan memory elements. A feedback cycle is defined as a feedback path from the output of a memory element to the input of said memory element.
摘要翻译：教导了一种修改用于部分扫描测试的数字集成电路的方法和装置，并且对电路的性能特征几乎没有或没有影响。说明性地，扫描存储器元件是基于它们消除电路中的反馈循环的能力以及由于包含扫描存储器元件而引起的潜在性能下降的考虑，从电路中的所有存储元件中选择的。反馈周期被定义为从存储元件的输出到所述存储器元件的输入的反馈路径。

10. 发明授权

US06463561B1 Almost full-scan BIST method and system having higher fault coverage and shorter test application time 有权
标题翻译：几乎全扫描BIST方法和系统具有较高的故障覆盖率和较短的测试应用时间
公开(公告)号：US06463561B1
公开(公告)日：2002-10-08
申请号：US09408371
申请日：1999-09-29
申请人： Sudipta Bhawmik , Kwang-Ting Cheng , Huan-Chih Tsai
发明人： Sudipta Bhawmik , Kwang-Ting Cheng , Huan-Chih Tsai
IPC分类号： G01R3128
CPC分类号： G01R31/318544 , G01R31/31707 , G01R31/318541
摘要： An almost full-scan method and system for detecting faults in circuits can achieve higher fault coverages and significantly shorter test application time as compared with full-scan techniques. A special flip-flop selection of strategy is further described which permits implementation of the almost full-scan BIST method and system.
摘要翻译：与全扫描技术相比，用于检测电路故障的几乎全扫描方法和系统可以实现更高的故障覆盖率，并显着缩短测试应用时间。进一步描述了一种特殊的触发器选择策略，其允许实现几乎全扫描的BIST方法和系统。

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