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1. 发明申请

US20050067055A1 Thin buried oxides by low-dose oxygen implantation into modified silicon 失效
标题翻译：通过低剂量氧注入到改性硅中的薄埋氧化物
公开(公告)号：US20050067055A1
公开(公告)日：2005-03-31
申请号：US10674647
申请日：2003-09-30
申请人： Kwang Choe , Keith Fogel , Siegfried Maurer , Ryan Mitchell , Devendra Sadana
发明人： Kwang Choe , Keith Fogel , Siegfried Maurer , Ryan Mitchell , Devendra Sadana
IPC分类号： H01L21/265 , H01L21/3063 , H01L21/316 , H01L21/762 , C23C8/36
CPC分类号： H01L21/76243 , H01L21/26533 , H01L21/3063 , H01L21/31662
摘要： A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.
摘要翻译：提供了一种制造在含Si的上层下方具有薄但均匀的掩埋氧化物区域的硅绝缘体（SOI）的方法。通过首先修饰含Si衬底的表面以包含大量的空位或空隙的浓度来制造SOI结构。接下来，含硅层通常但不总是形成在衬底顶上，然后使用低氧剂量将氧离子注入到结构中。然后将结构退火以将注入的氧离子转化成薄但均匀的热掩埋氧化物区域。

2. 发明申请

US20050056352A1 Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer 失效
标题翻译：通过掩埋多孔硅层的氧化形成绝缘体上硅结构的结构
公开(公告)号：US20050056352A1
公开(公告)日：2005-03-17
申请号：US10662028
申请日：2003-09-12
申请人： Stephen Bedell , Kwang Choe , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Kwang Choe , Keith Fogel , Devendra Sadana
IPC分类号： C22F1/10 , H01L21/20 , H01L21/762 , C22F1/00
CPC分类号： H01L21/76227 , C22F1/10 , H01L21/02378 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/76245 , H01L29/78603
摘要： A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.
摘要翻译：提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

3. 发明申请

US20050067294A1 SOI by oxidation of porous silicon 失效
标题翻译： SOI通过多孔硅的氧化
公开(公告)号：US20050067294A1
公开(公告)日：2005-03-31
申请号：US10674648
申请日：2003-09-30
申请人： Kwang Choe , Keith Fogel , Devendra Sadana
发明人： Kwang Choe , Keith Fogel , Devendra Sadana
IPC分类号： C25D7/12 , C25F3/04 , H01L21/316 , H01L21/762 , H01L21/786 , H01L21/84
CPC分类号： H01L21/76245 , C25F3/04
摘要： A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.
摘要翻译：提供了通过分级多孔Si的氧化制造SOI衬底结构的方法。通过首先将掺杂剂（p型或n型）注入到含Si衬底中，使用激活退火步骤激活掺杂剂，然后对含HF溶液中的注入和活化的掺杂剂区进行阳极化，形成渐变多孔Si。分级多孔Si具有相对粗糙的顶层和埋在顶层下方的细多孔层。在随后的氧化步骤中，精细埋入的多孔层被转化为掩埋氧化物，而粗顶层通过Si原子的表面迁移而结合成固体含Si的超层。

4. 发明申请

US20050170570A1 High electrical quality buried oxide in simox 审中-公开
标题翻译：高电气质量埋藏氧化物
公开(公告)号：US20050170570A1
公开(公告)日：2005-08-04
申请号：US10768341
申请日：2004-01-30
申请人： Joel DeSouza , Keith Fogel , Harold Hovel , Junedong Lee , Siegfried Maurer , Devendra Sadana , Dominic Schepis
发明人： Joel DeSouza , Keith Fogel , Harold Hovel , Junedong Lee , Siegfried Maurer , Devendra Sadana , Dominic Schepis
IPC分类号： H01L21/00 , H01L21/762 , H01L21/84
CPC分类号： H01L21/76243 , H01L21/84
摘要： A SIMOX (separation by implanted oxygen) process is provided that forms a silicon-on-insulator (SOI) substrate having a buried oxide with improved electrical properties. The process implements at least one of the following processing steps into SIMOX: (I) lowering of the oxygen ion dose in the base oxygen ion implant step; (II) off-setting the implant energy of the room temperature (RT) implant step to a value that is about 5 to about 20% lower than the base ion implant step; and (III) creating a soak cycle, i.e., pre-annealing step, prior to the internal oxidation anneal which allows dissolution of Si and SiOx precipitates in the oxygen implanted region. The temperature and time of the soak cycle as well as the base implant dose are critical in determining the final BOX quality.
摘要翻译：提供SIMOX（通过注入氧的分离）工艺，其形成具有改善的电性能的具有掩埋氧化物的绝缘体上硅（SOI）衬底。该方法将至少一个以下处理步骤实施到SIMOX中：（I）降低基氧离子注入步骤中的氧离子剂量; （II）将室温（RT）注入步骤的植入能量设置为比基础离子注入步骤低约5至约20％的值; 和（III）在内部氧化退火之前产生浸泡循环，即预退火步骤，其允许在氧注入区域中溶解Si和SiO x X沉淀。浸泡循环的温度和时间以及基础植入剂量对于确定最终BOX质量至关重要。

5. 发明申请

US20060027808A1 METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 有权
标题翻译：形成具有改善的导热性的应变硅材料的方法
公开(公告)号：US20060027808A1
公开(公告)日：2006-02-09
申请号：US10710826
申请日：2004-08-05
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

6. 发明申请

US20070281439A1 Techniques for Layer Transfer Processing 审中-公开
标题翻译：层传输处理技术
公开(公告)号：US20070281439A1
公开(公告)日：2007-12-06
申请号：US11840389
申请日：2007-08-17
申请人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
发明人： Stephen Bedell , Keith Fogel , Bruce Furman , Sampath Purushothaman , Devendra Sadana , Anna Topol
IPC分类号： H01L21/30 , H01L21/00
CPC分类号： H01L21/76259 , Y10T428/249961
摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a thee dimensional integrated structure is provided.
摘要翻译：提供了制造半导体器件的技术。一方面，提供了层转移结构。层转移结构包括具有调谐孔隙度的多孔区域的载体衬底以及限定分离平面的注入物质的组合。另一方面，提供了一种形成层转移结构的方法。另一方面，提供了一种形成一维一体结构的方法。

7. 发明申请

US20070164356A1 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US20070164356A1
公开(公告)日：2007-07-19
申请号：US11332564
申请日：2006-01-13
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

8. 发明申请

US20060154429A1 Method for fabricating low-defect-density changed orientation Si 失效
标题翻译：制造低缺陷密度变化取向Si的方法
公开(公告)号：US20060154429A1
公开(公告)日：2006-07-13
申请号：US11031142
申请日：2005-01-07
申请人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
发明人： Joel de Souza , Keith Fogel , John Ott , Devendra Sadana , Katherine Saenger
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/2022
摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.
摘要翻译：本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向具有不同的方向。更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶非晶层的原始方向。本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。

9. 发明申请

US20060081837A1 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
公开(公告)号：US20060081837A1
公开(公告)日：2006-04-20
申请号：US11293774
申请日：2005-12-02
申请人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
发明人： Stephen Bedell , Anthony Domenicucci , Keith Fogel , Effendi Leobandung , Devendra Sadana
IPC分类号： H01L31/109
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

10. 发明申请

US20050048778A1 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US20050048778A1
公开(公告)日：2005-03-03
申请号：US10654232
申请日：2003-09-03
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana
IPC分类号： H01L29/161 , C30B29/52 , C30B31/02 , H01L21/02 , H01L21/20 , H01L21/205 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/04 , C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

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