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1. 发明申请

US20050285218A1 Method of forming high voltage devices with retrograde well 有权
标题翻译：用逆行井形成高压装置的方法
公开(公告)号：US20050285218A1
公开(公告)日：2005-12-29
申请号：US10877450
申请日：2004-06-25
申请人： Kuo-Ming Wu , Chen-Bau Wu , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Kuo-Ming Wu , Chen-Bau Wu , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L29/00 , H01L29/08 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/7835
摘要： A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.
摘要翻译：公开了具有逆行井的高压装置。该器件包括衬底，形成在衬底上的栅极区域和位于栅极区域旁边的衬底中的逆行阱，其中逆行阱降低衬底表面上的掺杂剂浓度，从而最小化对栅极区域的损害。

2. 发明授权

US07221021B2 Method of forming high voltage devices with retrograde well 有权
标题翻译：用逆行井形成高压装置的方法
公开(公告)号：US07221021B2
公开(公告)日：2007-05-22
申请号：US10877450
申请日：2004-06-25
申请人： Kuo-Ming Wu , Chen-Bau Wu , Ruey-Hsin Liu , Shun-Liang Hsu
发明人： Kuo-Ming Wu , Chen-Bau Wu , Ruey-Hsin Liu , Shun-Liang Hsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/0847 , H01L29/7835
摘要： A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.
摘要翻译：公开了具有逆行井的高压装置。该器件包括衬底，形成在衬底上的栅极区域和位于栅极区域旁边的衬底中的逆行阱，其中逆行阱降低衬底表面上的掺杂剂浓度，从而最小化对栅极区域的损害。

3. 发明申请

US20050112824A1 Method of forming gate oxide layers with multiple thicknesses on substrate 审中-公开
标题翻译：在衬底上形成多个厚度的栅氧化层的方法
公开(公告)号：US20050112824A1
公开(公告)日：2005-05-26
申请号：US10723794
申请日：2003-11-26
申请人： Yu-Chang Jong , Ruey-Hsin Liu , Yi-Chun Lin , Shun-Liang Hsu , Chen-Bau Wu , Kuo-Ming Wu
发明人： Yu-Chang Jong , Ruey-Hsin Liu , Yi-Chun Lin , Shun-Liang Hsu , Chen-Bau Wu , Kuo-Ming Wu
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/823481
摘要： A method of forming gate dielectric layers with various thicknesses on a substrate. At least a first active region and a second active region are provided on the substrate. A first thermal oxide layer is formed on the substrate. A blanket dielectric layer with a first thickness is deposited overlying the substrate. The dielectric layer and the underlying first thermal oxide layer on the second active region are removed to expose the substrate. A second thermal oxide layer with a second thickness less than the first thickness is formed on the second active region. A first gate is formed on the dielectric layer on the first active region and a second gate is formed on the second thermal oxide layer on the second active region.
摘要翻译：在基板上形成各种厚度的栅极电介质层的方法。至少第一有源区和第二有源区设置在衬底上。在基板上形成第一热氧化层。具有第一厚度的覆盖介电层沉积在衬底上。去除第二有源区上的电介质层和下面的第一热氧化物层以露出衬底。在第二有源区上形成第二厚度小于第一厚度的第二热氧化层。第一栅极形成在第一有源区上的电介质层上，第二栅极形成在第二有源区上的第二热氧化物层上。

4. 发明授权

US07602037B2 High voltage semiconductor devices and methods for fabricating the same 有权
标题翻译：高压半导体器件及其制造方法
公开(公告)号：US07602037B2
公开(公告)日：2009-10-13
申请号：US11692213
申请日：2007-03-28
申请人： Yi-Chun Lin , Chi-Chih Chen , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Chi-Chih Chen , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L27/088 , H01L29/06
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/0886 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.
摘要翻译：能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。在掺杂体区和阱区之间不存在P-N结。

5. 发明授权

US08415211B2 Semiconductor device, method of fabricating the same, and patterning mask utilizied by the method 有权
标题翻译：半导体装置及其制造方法，以及通过该方法利用的图案化掩模
公开(公告)号：US08415211B2
公开(公告)日：2013-04-09
申请号：US13301657
申请日：2011-11-21
申请人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L21/8234
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66681 , Y10T428/24802
摘要： A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.
摘要翻译：半导体器件。该器件包括由衬底上的隔离结构隔离的有源区。该器件还包括延伸跨过有源区并覆盖衬底的栅电极，一对源极区和漏极区，设置在有源区中的衬底上的栅电极的任一侧上，栅极电介质层位于基板和栅电极。栅介质层包括相对较厚的高电压（HV）电介质部分和相对较薄的低电压（LV）电介质部分，其中HV电介质部分占据漏区，隔离结构和栅极之间的第一交点电极，以及源区域，隔离结构和栅电极之间的第二交叉点。

6. 发明授权

US08093663B2 Semiconductor device, method of fabricating the same, and patterning mask utilized by the method 有权
标题翻译：半导体装置及其制造方法以及由该方法使用的图案化掩模
公开(公告)号：US08093663B2
公开(公告)日：2012-01-10
申请号：US11430243
申请日：2006-05-09
申请人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L29/423
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66681 , Y10T428/24802
摘要： A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.
摘要翻译：半导体器件。该器件包括由衬底上的隔离结构隔离的有源区。该器件还包括延伸跨过有源区并覆盖衬底的栅电极，一对源极区和漏极区，设置在有源区中的衬底上的栅电极的任一侧上，栅电介质层位于基板和栅电极。栅介质层包括相对较厚的高电压（HV）电介质部分和相对较薄的低电压（LV）电介质部分，其中HV电介质部分占据漏区，隔离结构和栅极之间的第一交点电极，以及源区域，隔离结构和栅电极之间的第二交叉点。

7. 发明申请

US20080237703A1 HIGH VOLTAGE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：高电压半导体器件及其制造方法
公开(公告)号：US20080237703A1
公开(公告)日：2008-10-02
申请号：US11692213
申请日：2007-03-28
申请人： Yi-Chun Lin , Chi-Chih Chen , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Chi-Chih Chen , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/0886 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.
摘要翻译：能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。在掺杂体区和阱区之间不存在P-N结。

8. 发明申请

US20070181941A1 High voltage semiconductor devices and methods for fabricating the same 有权
标题翻译：高压半导体器件及其制造方法
公开(公告)号：US20070181941A1
公开(公告)日：2007-08-09
申请号：US11351154
申请日：2006-02-09
申请人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/42368 , H01L29/66681
摘要： High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying the substrate, comprising a gate dielectric layer and a gate electrode formed thereon. A channel well and a second well are formed in portions of the first well. A source region is formed in a portion of the channel well. A drain region is formed in a portion of the second well, wherein the gate dielectric layer comprises a relatively thinner portion at one end of the gate stack adjacent to the source region and a relatively thicker portion at one end of the gate stack adjacent to and directly contacts the drain region.
摘要翻译：提供了高压半导体器件及其制造方法。能够进行高压操作的半导体器件的示例性实施例，包括其中形成有第一阱的衬底。形成覆盖在衬底上的栅叠层，包括形成在其上的栅介质层和栅电极。在第一井的部分中形成通道井和第二井。源区域形成在通道井的一部分中。漏极区域形成在第二阱的一部分中，其中栅极电介质层包括邻近源极区域的栅极堆叠的一端处的相对较薄的部分，以及邻近栅极堆叠的一端的相对较厚的部分，直接接触漏区。

9. 发明申请

US20070262369A1 Semiconductor device, method of fabricating the same, and patterning mask utilizied by the method 有权
标题翻译：半导体器件及其制造方法，以及通过该方法利用的图案化掩模
公开(公告)号：US20070262369A1
公开(公告)日：2007-11-15
申请号：US11430243
申请日：2006-05-09
申请人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L29/788 , H01L21/337
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66681 , Y10T428/24802
摘要： A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.
摘要翻译：半导体器件。该器件包括由衬底上的隔离结构隔离的有源区。该器件还包括延伸跨过有源区并覆盖衬底的栅电极，一对源极区和漏极区，设置在有源区中的衬底上的栅电极的任一侧上，栅极电介质层位于基板和栅电极。栅介质层包括相对较厚的高电压（HV）电介质部分和相对较薄的低电压（LV）电介质部分，其中HV电介质部分占据漏区，隔离结构和栅极之间的第一交点电极，以及源区域，隔离结构和栅电极之间的第二交叉点。

10. 发明申请

US20120061737A1 SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND PATTERNING MASK UTILIZIED BY THE METHOD 有权
标题翻译：半导体器件，其制造方法以及由该方法使用的掩模图案
公开(公告)号：US20120061737A1
公开(公告)日：2012-03-15
申请号：US13301657
申请日：2011-11-21
申请人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
发明人： Yi-Chun Lin , Kuo-Ming Wu , Ruey-Hsin Liu
IPC分类号： H01L29/78 , B32B3/00 , H01L21/336 , B82Y99/00
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/42368 , H01L29/66681 , Y10T428/24802
摘要： A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, disposed on either side of the gate electrode on the substrate in the active area, and a gate dielectric layer disposed between the substrate and the gate electrode. The gate dielectric layer comprises a relatively-thicker high voltage (HV) dielectric portion and a relatively-thinner low voltage (LV) dielectric portion, wherein the HV dielectric portion occupies a first intersection among the drain region, the isolation structure, and the gate electrode, and a second intersection among the source region, the isolation structure, and the gate electrode.
摘要翻译：半导体器件。该器件包括由衬底上的隔离结构隔离的有源区。该器件还包括延伸跨过有源区并覆盖衬底的栅电极，一对源极区和漏极区，设置在有源区中的衬底上的栅电极的任一侧上，栅电介质层位于基板和栅电极。栅介质层包括相对较厚的高电压（HV）电介质部分和相对较薄的低电压（LV）电介质部分，其中HV电介质部分占据漏区，隔离结构和栅极之间的第一交点电极，以及源区域，隔离结构和栅电极之间的第二交叉点。

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