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1. 发明授权

US06707079B2 Twin MONOS cell fabrication method and array organization 有权
标题翻译：双MONOS电池制造方法和阵列组织
公开(公告)号：US06707079B2
公开(公告)日：2004-03-16
申请号：US10356446
申请日：2003-02-03
申请人： Kumihiro Satoh , Seiki Ogura , Tomoya Saito
发明人： Kumihiro Satoh , Seiki Ogura , Tomoya Saito
IPC分类号： H01L2976
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573 , H01L29/66833 , H01L29/7923 , Y10S257/906 , Y10S438/954
摘要： Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods, i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication. ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel. Two embodiments of the present invention are disclosed.
摘要翻译：在本发明中提出了一种用于集成双MONOS存储单元阵列和CMOS逻辑器件电路的高密度双MONOS存储器件的制造方法及其阵列组织。本发明由两种制造方法组成：i）同时定义存储器栅极和逻辑门，从而改进工艺集成方案，以便更容易和更可靠的制造.ii）位线跨越字门和控制栅极。本发明着重于降低寄生薄片电阻以实现高速同时保持低的制造成本。双MONOS单元将存储器存储在选择栅极的两个侧壁上的两个共享控制栅极下的两个氮化物存储单元元件中。该方法适用于具有平坦通道的设备和/或具有步进通道的设备。本发明的两个实施例被公开。

2. 发明授权

US08174885B2 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US08174885B2
公开(公告)日：2012-05-08
申请号：US13068066
申请日：2011-05-02
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新型读取方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门用于对选定的存储单元进行寻址

3. 发明授权

US07391653B2 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US07391653B2
公开(公告)日：2008-06-24
申请号：US11409376
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0475 , H01L27/115 , H01L29/7923
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

4. 发明授权

US07190603B2 Nonvolatile memory array organization and usage 有权
标题翻译：非易失性存储器阵列的组织和使用
公开(公告)号：US07190603B2
公开(公告)日：2007-03-13
申请号：US11124221
申请日：2005-05-06
申请人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C5/06
CPC分类号： G11C16/0475 , G11C5/025 , G11C16/16 , G11C16/24 , H01L27/115
摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.
摘要翻译：实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。该装置包括一个存储单元阵列区域，其中多个C列和R行的存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织由沿第一方向运行的R行字线组成，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

5. 发明申请

US20060227622A1 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US20060227622A1
公开(公告)日：2006-10-12
申请号：US11409382
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/14 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/792
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

6. 发明申请

US20060221706A1 Twin insulator charge storage device operation and its fabrication method 有权
公开(公告)号：US20060221706A1
公开(公告)日：2006-10-05
申请号：US11409372
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/14 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/792
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

7. 发明授权

US06900098B1 Twin insulator charge storage device operation and its fabrication method 有权
标题翻译：双绝缘子电荷存储装置的操作及其制作方法
公开(公告)号：US06900098B1
公开(公告)日：2005-05-31
申请号：US10685873
申请日：2003-10-15
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L29/02 , H01L29/423 , H01L29/792 , H01L47/00
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
摘要翻译：本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。控制栅极和字栅之间的垂直绝缘体不包括氮化物层。这样可以防止电子捕获的问题。可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

8. 发明授权

US06759290B2 Stitch and select implementation in twin MONOS array 有权
公开(公告)号：US06759290B2
公开(公告)日：2004-07-06
申请号：US10107002
申请日：2002-03-26
申请人： Tomoko Ogura , Tomoya Saito , Seiki Ogura , Kimihiro Satoh
发明人： Tomoko Ogura , Tomoya Saito , Seiki Ogura , Kimihiro Satoh
IPC分类号： H01L218238
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

9. 发明授权

US06418062B1 Erasing methods by hot hole injection to carrier trap sites of a nonvolatile memory 有权
标题翻译：通过热空穴注入去除非易失性存储器的载波陷阱位置的方法
公开(公告)号：US06418062B1
公开(公告)日：2002-07-09
申请号：US09795186
申请日：2001-03-01
申请人： Yutaka Hayashi , Seiki Ogura , Tomoya Saito
发明人： Yutaka Hayashi , Seiki Ogura , Tomoya Saito
IPC分类号： G11C1134
CPC分类号： G11C16/14
摘要： A method of stably and uniformly erasing a non-volatile memory or memory array in a gate insulator in which carrier-trapping sites for carrier storage are furnished is described. A first method of the invention is the application of a discharge pulse(s) to a gate after erasure where the discharge pulse(s) discharges unstable holes injected into the gate insulator. A second method of the invention is injection of electrons into the trap sites of all the cells in a memory array to be erased before erasure. This makes Vth distribution across the memory array uniform after erasure. A third method of the invention is a reduced bias approach to erase stably the electrons stored in the trap sites. This includes not only literally “erase,” but also “annihilate or neutralize” trapped electron charge by hole charge.
摘要翻译：描述了在其中提供用于载体存储的载流子捕获位点的栅绝缘体中稳定且均匀地擦除非易失性存储器或存储器阵列的方法。本发明的第一种方法是在擦除之后将放电脉冲施加到栅极，其中放电脉冲放电注入到栅极绝缘体中的不稳定空穴。本发明的第二种方法是将电子注入存储器阵列中的所有细胞的陷阱位点，以在擦除之前被擦除。这使得擦除之后，跨存储器阵列的Vth分布均匀。本发明的第三种方法是减少偏压方法，以便稳定地消除存储在捕获位点中的电子。这不仅包括字面上的“擦除”，还包括通过孔电荷“消除或中和”捕获的电子电荷。

10. 发明授权

US07382662B2 Twin insulator charge storage device operation and its fabrication method 有权
标题翻译：双绝缘子电荷存储装置的操作及其制作方法
公开(公告)号：US07382662B2
公开(公告)日：2008-06-03
申请号：US11409247
申请日：2006-04-21
申请人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C11/34 , H01L23/58
CPC分类号： H01L21/28282 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/42364 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
摘要翻译：本发明提出了改进的双MONOS存储器件及其制造方法。 ONO层水平自对准控制门。控制栅极和字栅之间的垂直绝缘体不包括氮化物层。这样可以防止电子捕获的问题。可以制造器件以通过ONO绝缘体的顶部或底部氧化物层拉出电子。该器件还包括在控制栅极之间的升高的存储器位扩散以减小位阻。双MONOS存储器阵列可以通过本发明的方法嵌入到标准CMOS电路中。

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