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1. 发明申请

US20050248984A1 Nonvolatile memory array organization and usage 有权
标题翻译：非易失性存储器阵列的组织和使用
公开(公告)号：US20050248984A1
公开(公告)日：2005-11-10
申请号：US11124221
申请日：2005-05-06
申请人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C5/02 , G11C16/04 , G11C16/16 , G11C16/24 , H01L27/115
CPC分类号： G11C16/0475 , G11C5/025 , G11C16/16 , G11C16/24 , H01L27/115
摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device comprises a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.
摘要翻译：实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。该装置包括存储单元阵列区域，其中多个C列和R行存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织包括沿第一方向运行的R行字线，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

2. 发明授权

US07190603B2 Nonvolatile memory array organization and usage 有权
标题翻译：非易失性存储器阵列的组织和使用
公开(公告)号：US07190603B2
公开(公告)日：2007-03-13
申请号：US11124221
申请日：2005-05-06
申请人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
发明人： Seiki Ogura , Tomoko Ogura , Ki-Tae Park , Nori Ogura , Kimihiro Satoh , Tomoya Saito
IPC分类号： G11C5/06
CPC分类号： G11C16/0475 , G11C5/025 , G11C16/16 , G11C16/24 , H01L27/115
摘要： A non-volatile semiconductor storage device array organization for wide program operations is achieved. The device includes a memory cell array region in which a plurality of C columns and R rows of memory cells comprise one UNIT, arranged in a “diffusion bit” array organization which is comprised of R rows of word lines running in a first direction, and C columns of diffusion sub bit lines running in a second direction, and C columns of sub control gate lines running in the same second direction and a sense amplifier/page buffer area shared by several UNIT's through a bit decode circuit, wherein the diffusion sub bit lines in each of the UNIT's are connected to main bit lines which are in turn connected to the sense amplifier/page buffer area, wherein the bit decode circuit selects one diffusion sub bit line column of memory cells in every E columns.
摘要翻译：实现了用于广泛程序操作的非易失性半导体存储器件阵列组织。该装置包括一个存储单元阵列区域，其中多个C列和R行的存储单元包括一个单元，以“扩散位”阵列组织排列，该阵列组织由沿第一方向运行的R行字线组成，以及 C列的第二方向上延伸的扩散子位线，以及在相同的第二方向上运行的子控制栅极线的C列以及由多个单元通过位解码电路共享的读出放大器/页缓冲区，其中扩散子位每个单元中的线连接到主位线，主位线又连接到读出放大器/页面缓冲区域，其中位解码电路在每个E列中选择存储器单元的一个扩散子位线列。

3. 发明申请

US20070047307A1 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US20070047307A1
公开(公告)日：2007-03-01
申请号：US11215418
申请日：2005-08-30
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门被用于寻址选定的存储单元。

4. 发明授权

US08174885B2 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US08174885B2
公开(公告)日：2012-05-08
申请号：US13068066
申请日：2011-05-02
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.teh
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新型读取方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门用于对选定的存储单元进行寻址

5. 发明申请

US20110205798A1 High speed operation method for Twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US20110205798A1
公开(公告)日：2011-08-25
申请号：US13068066
申请日：2011-05-02
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C16/26 , G11C16/04 , G11C16/28
CPC分类号： G11C16/0475
摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门被用于寻址选定的存储单元。

6. 发明授权

US07936604B2 High speed operation method for twin MONOS metal bit array 有权
标题翻译：双MONOS金属钻头阵列的高速运行方式
公开(公告)号：US07936604B2
公开(公告)日：2011-05-03
申请号：US11215418
申请日：2005-08-30
申请人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
发明人： Tomoko Ogura , Nori Ogura , Seiki Ogura , Tomoya Saito , Yoshitaka Baba
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.
摘要翻译：本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。在本发明的第一实施例中，替代控制栅极被设置在相同的电压。在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。在两个实施例中，位线和字门被用于寻址选定的存储单元。

7. 发明授权

US07006378B1 Array architecture and operation methods for a nonvolatile memory 有权
标题翻译：非易失性存储器的阵列架构和操作方法
公开(公告)号：US07006378B1
公开(公告)日：2006-02-28
申请号：US10742987
申请日：2003-12-22
申请人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
发明人： Tomoya Saito , Tomoko Ogura , Kimihiro Satoh , Seiki Ogura
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A nonvolatile memory device is achieved. The device comprises a string of MONOS cells connected drain to source. Each MONOS cell comprises a wordline gate overlying a channel region in a substrate. First and second control gates each overlying a channel region in the substrate. The wordline gate channel region is laterally between first and second control gate channel regions. An ONO layer is vertically between the control gates and the substrate. The nitride layer of the ONO layer forms a charge storage site for each control gate. First and second doped regions, forming a source and a drain, are in the substrate. The wordline gate channel region and the control gate channel regions are between the first doped region and the second doped region. First and second transistors connect the topmost MONOS cell to a first bit line and the bottom most MONOS cell to a second bit line.
摘要翻译：实现非易失性存储器件。该装置包括一串连接到源极的MONOS电池。每个MONOS单元包括覆盖衬底中的沟道区的字线门。第一和第二控制栅极，每个覆盖衬底中的沟道区域。字线栅极沟道区域横向在第一和第二控制栅极沟道区域之间。 ONO层在控制栅极和衬底之间垂直。 ONO层的氮化物层形成每个控制栅极的电荷存储位置。在衬底中形成源极和漏极的第一和第二掺杂区域。字线栅极沟道区和控制栅沟道区在第一掺杂区和第二掺杂区之间。第一和第二晶体管将最上面的MONOS单元连接到第一位线，将最底部的MONOS单元连接到第二位线。

8. 发明授权

US06670240B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06670240B2
公开(公告)日：2003-12-30
申请号：US10218210
申请日：2002-08-13
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L21336
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

9. 发明授权

US06998658B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06998658B2
公开(公告)日：2006-02-14
申请号：US10697925
申请日：2003-10-30
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

10. 发明授权

US06825084B2 Twin NAND device structure, array operations and fabrication method 有权
公开(公告)号：US06825084B2
公开(公告)日：2004-11-30
申请号：US10697520
申请日：2003-10-30
申请人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
发明人： Seiki Ogura , Tomoko Ogura , Tomoya Saito , Kimihiro Satoh
IPC分类号： H01L21336
CPC分类号： G11C11/5671 , G11C16/0475 , H01L27/115 , H01L27/11568
摘要： A method for making a twin MONOS memory array is described where two nitride storage sites lay under the memory cell word gate. The fabrication techniques incorporate self alignment techniques to produce a small cell in which N+ diffusion the nitride storage sites are defined by sidewalls. The memory cell is used in an NAND array where the memory operations are controlled by voltages on the word lines and column selectors. Each storage site within the memory cell is separately programmed and read by application of voltages to the selected cell through the selected word line whereas the unselected word lines are used to pass drain and source voltages to the selected cell from upper and lower column voltages.

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