专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5642252A Insulated gate semiconductor device and driving circuit device and electronic system both using the same 失效
标题翻译：绝缘栅半导体器件和驱动电路器件和电子系统均采用相同的方式
公开(公告)号：US5642252A
公开(公告)日：1997-06-24
申请号：US288729
申请日：1994-08-15
申请人： Kozo Sakamoto , Isao Yoshida , Shigeo Otaka , Tetsuo Iijima , Harutora Shono , Ken Uchid , Masayoshi Kobayashi , Hideki Tsunoda
发明人： Kozo Sakamoto , Isao Yoshida , Shigeo Otaka , Tetsuo Iijima , Harutora Shono , Ken Uchid , Masayoshi Kobayashi , Hideki Tsunoda
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/78 , H02H5/04 , H03K17/08 , H03K17/082 , H02H3/00
CPC分类号： H03K17/0822 , H01L27/0248 , H01L27/0251 , H01L27/0255 , H01L29/7803 , H01L29/7804 , H02H5/044 , H01L29/0696 , H03K2017/0806
摘要： An improvement in conditions that protective functions of an insulated gate semiconductor device with a protection circuit incorporated therein are performed, an improvement in the cutoff of heating, the prevention of malfunctions and an improvement in ease of usage can be achieved.The insulated gate semiconductor device of the present invention comprises a power insulated gate semiconductor element (M9), at least one MOSFET (M1 through M7) for a protection circuit, for controlling the power insulated gate semiconductor element, a constant-voltage circuit using forward voltages developed across diodes (D2a through D2f) for the constant-voltage circuit, and voltage restricting diodes (D1 and D0a through D0d) for controlling the upper limit of a power supply voltage of the constant-voltage circuit. Power to be supplied to the voltage restricting diodes is supplied from an external gate terminal of the power insulated gate semiconductor element.The present invention can bring about an advantageous effect that an improvement in reliability of the insulated gate semiconductor device and an improvement in the ease of use can be achieved.
摘要翻译：可以实现具有并入其中的保护电路的绝缘栅半导体器件的保护功能的条件的改善，可以提高加热截止，防止故障和提高易用性。本发明的绝缘栅半导体器件包括功率绝缘栅极半导体元件（M9），用于保护电路的至少一个MOSFET（M1至M7），用于控制功率绝缘栅极半导体元件，使用正向的恒压电路用于恒压电路的二极管（D2a至D2f）上产生的电压以及用于控制恒压电路的电源电压的上限的电压限制二极管（D1和D0a至D0d）。供电到限压二极管的功率从功率绝缘栅极半导体元件的外部栅极端子提供。本发明可以实现提高绝缘栅极半导体器件的可靠性和提高易用性的有利效果。

2. 发明授权

US4831424A Insulated gate semiconductor device with back-to-back diodes 失效
标题翻译：具有背对背二极管的绝缘栅半导体器件
公开(公告)号：US4831424A
公开(公告)日：1989-05-16
申请号：US62388
申请日：1987-06-15
申请人： Isao Yoshida , Takeaki Okabe , Mitsuo Ito , Kazutoshi Ashikawa , Tetsuo Iijima
发明人： Isao Yoshida , Takeaki Okabe , Mitsuo Ito , Kazutoshi Ashikawa , Tetsuo Iijima
IPC分类号： H03F1/52 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/78 , H02H7/20 , H03F1/42
CPC分类号： H01L29/7808 , H01L27/0255 , H01L29/7811 , H01L29/0692 , H01L29/866 , H01L2924/0002
摘要： An insulated gate semiconductor device contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.
摘要翻译：绝缘栅半导体器件包含用于保护绝缘栅场效应晶体管的栅电极的保护元件。保护元件由与绝缘栅场效应晶体管的栅电极相同的半导体层形成，并与形成在半导体基板的表面上的绝缘膜上的栅电极一体形成。

3. 发明授权

US4688323A Method for fabricating vertical MOSFETs 失效
标题翻译：制造垂直MOSFET的方法
公开(公告)号：US4688323A
公开(公告)日：1987-08-25
申请号：US793243
申请日：1985-10-31
申请人： Isao Yoshida , Takeaki Okabe , Mitsuo Ito , Kazutoshi Ashikawa , Tetsuo Iijima
发明人： Isao Yoshida , Takeaki Okabe , Mitsuo Ito , Kazutoshi Ashikawa , Tetsuo Iijima
IPC分类号： H03F1/52 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/78 , H02H7/20 , H03F1/42 , H01L21/425 , H01L21/72
CPC分类号： H01L29/7808 , H01L27/0255 , H01L29/7811 , H01L29/0692 , H01L29/866 , H01L2924/0002
摘要： A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.
摘要翻译：一种用于制造垂直MOSFET的方法，其包含用于保护绝缘栅场效应晶体管的栅电极的保护元件。保护元件由与绝缘栅场效应晶体管的栅电极相同的半导体层形成，并与形成在半导体基板的表面上的绝缘膜上的栅电极一体形成。

4. 发明申请

US20110089558A1 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110089558A1
公开(公告)日：2011-04-21
申请号：US12906122
申请日：2010-10-17
申请人： Akira MUTO , Akira Mishima , Takuro Kanazawa , Ochi Kentaro , Tetsuo Iijima , Katsuo Ishizaka
发明人： Akira MUTO , Akira Mishima , Takuro Kanazawa , Ochi Kentaro , Tetsuo Iijima , Katsuo Ishizaka
IPC分类号： H01L23/36 , H01L21/50 , H01L23/50
CPC分类号： H01L25/072 , H01L23/3121 , H01L24/37 , H01L24/40 , H01L25/115 , H01L25/16 , H01L2224/32225 , H01L2224/37147 , H01L2224/40095 , H01L2224/40137 , H01L2224/73221 , H01L2224/83801 , H01L2224/84801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01058 , H01L2924/01074 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12036 , H01L2924/13055 , H01L2924/1306 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： There is provided a technology capable of reducing the mounting burden on the part of a customer which is a recipient of a package. Over a metal board, a single package and another single package are mounted together via an insulation adhesion sheet, thereby to form one composite package. As a result, as compared with the case where six single packages are mounted, the number of packages to be mounted is smaller in the case where three sets of the composite packages are mounted. This can reduce the mounting burden on the part of a customer.
摘要翻译：提供了能够减少作为包装的接收者的顾客的部分的安装负担的技术。在金属板上，单个包装和另一个单一包装通过绝缘粘合片安装在一起，从而形成一个复合包装。结果，与安装六个单个包装件的情况相比，在安装三组复合包装的情况下，要安装的包装件的数量较小。这可以减少客户的安装负担。

5. 发明授权

US5656498A Freeze-dried blood cells, stem cells and platelets, and manufacturing method for the same 失效
标题翻译：冷冻干细胞，干细胞和血小板及其制造方法相同
公开(公告)号：US5656498A
公开(公告)日：1997-08-12
申请号：US390957
申请日：1995-02-21
申请人： Tetsuo Iijima , Yoshikazu Ishii , Nobuhiro Funakoshi , Keiji Okada
发明人： Tetsuo Iijima , Yoshikazu Ishii , Nobuhiro Funakoshi , Keiji Okada
IPC分类号： A01N1/02 , A61K35/14 , A61K35/16 , A61K35/18 , A61K35/19 , A61K35/28 , G01N31/00
CPC分类号： A01N1/0221 , A01N1/02 , A61K35/16 , A61K35/19 , A61K35/28 , Y10T436/10 , Y10T436/101666
摘要： The present invention provides a method for manufacturing freeze-dried blood cells, stem cells and platelets comprising the steps of: pre-treating a liquid selected from the group consisting of blood including blood cells, bone marrow fluid (hemopoietic stem cells), and platelets in blood plasma, with a solution containing at least one substance selected from the group consisting of saccharide, biopolymer, acid and acid salt; conducting granulation of the aforementioned pre-treated liquid into a granules of a predetermined size; performing rapid cooling of the granules; and drying the resultant frozen material by sublimation of the water content contained therein.
摘要翻译：本发明提供一种制造冷冻干燥血细胞，干细胞和血小板的方法，包括以下步骤：预先处理选自血细胞，骨髓液（造血干细胞）和血小板在血浆中，含有至少一种选自由糖，生物聚合物，酸和酸盐组成的组的物质的溶液; 将上述预处理液体造粒成规定尺寸的颗粒; 进行颗粒的快速冷却; 并通过升华其中含有的含水量来干燥所得的冷冻材料。

6. 发明授权

US5397914A Power transistor device including power transistors in darlington connection and zener diode which is coupled between collector and base of power transistors and which is formed in polysilicon film 失效
标题翻译：功率晶体管器件包括达林顿连接中的功率晶体管和齐纳二极管，其耦合在功率晶体管的集电极和基极之间，并且形成在多晶硅膜
公开(公告)号：US5397914A
公开(公告)日：1995-03-14
申请号：US52836
申请日：1993-04-27
申请人： Minoru Suda , Masatoshi Nakasu , Tetsuo Iijima
发明人： Minoru Suda , Masatoshi Nakasu , Tetsuo Iijima
IPC分类号： H01L27/082 , H02H9/04 , H02H9/02 , G05F1/613 , H01L27/02
CPC分类号： H02H9/047 , H01L27/0825
摘要： In a transistor where collector is connected to an inductive load and switching current flows, a Zener diode comprising structure of plural pn-junctions constituted in series form to a polysilicon is provided between collector and base. Further MOSFET is switch-controlled by control voltage formed based on Zener current flowing through the Zener diode, and current path in parallel form to the Zener diode is constituted. Since temperature characteristic coefficient of a Zener diode formed in a polysilicon film is very small, the reverse voltage generated in the inductive load can be set to stable voltage in spite of the temperature variation. Further the MOSFET is provided in parallel form, thereby relatively large ON-resistance value of the Zener diode can be decreased.
摘要翻译：在集电极连接到感性负载并且开关电流流动的晶体管中，在集电极和基极之间提供包括串联形成多晶硅的多个pn结的结构的齐纳二极管。另外的MOSFET由基于流过齐纳二极管的齐纳二次电流形成的控制电压进行开关控制，构成并联形式的齐纳二极管的电流路径。由于形成在多晶硅膜中的齐纳二极管的温度特性系数非常小，所以在电感负载中产生的反向电压可以设定为稳定的电压，尽管温度变化。此外，MOSFET以并行形式提供，由此可以减小齐纳二极管的相对大的导通电阻值。

7. 发明授权

US08035222B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08035222B2
公开(公告)日：2011-10-11
申请号：US12968534
申请日：2010-12-15
申请人： Kentaro Ochi , Akira Mishima , Takuro Kanazawa , Tetsuo Iijima , Katsuo Ishizaka , Norio Kido
发明人： Kentaro Ochi , Akira Mishima , Takuro Kanazawa , Tetsuo Iijima , Katsuo Ishizaka , Norio Kido
IPC分类号： H01L23/34
CPC分类号： H01L23/3107 , H01L23/49568 , H01L23/49575 , H01L24/33 , H01L25/115 , H01L2224/32245 , H01L2924/1301 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.
摘要翻译：提供了通过使用半导体封装形成的半导体器件。半导体器件包括在感应导体上相邻布置的两个半导体封装。两个半导体封装的端子由第三引线连接。第三引线被布置成基本上平行于感应导体。接头部分处的引线例如具有弯曲结构，并且第三引线布置成靠近感应导体。

8. 发明申请

US20080149972A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080149972A1
公开(公告)日：2008-06-26
申请号：US11954110
申请日：2007-12-11
申请人： Katuo Ishizaka , Tetsuo Iijima
发明人： Katuo Ishizaka , Tetsuo Iijima
IPC分类号： H01L29/94
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0869 , H01L2224/0603 , H01L2224/48247 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.
摘要翻译：垂直功率MOSFET的导通电阻和漏电流将被减小。在具有纵向和横向地布置在半导体衬底的主表面上的单元MOSFET（单元）的垂直高击穿电压MOSFET中，单元被制成四边形形状，并且在每个单元中，其内端部暴露于四边形源接触孔的内部分别布置并对应于四边形的每一侧。每个源极区域是梯形的，并且梯形的下侧位于栅电极（栅极绝缘膜）的下方，而梯形的上侧部分暴露于源极接触孔的内部。四个源区域由四边形的对角区域彼此分开。

9. 发明授权

US07312501B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07312501B2
公开(公告)日：2007-12-25
申请号：US11030094
申请日：2005-01-07
申请人： Katuo Ishizaka , Tetsuo Iijima
发明人： Katuo Ishizaka , Tetsuo Iijima
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/0869 , H01L2224/0603 , H01L2224/48247 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made quadrangular in shape, and in each of the cells, source regions whose inner end portions are exposed to the interior of a quadrangular source contact hole are arranged separately and correspondingly to each side of the quadrangle. Each source region is trapezoidal in shape, and a lower side of the trapezoid is positioned below a gate electrode (gate insulating film), while an upper side portion of the trapezoid is exposed to the interior of the source contact hole. The four source regions are separated from one another by diagonal regions of the quadrangle.
摘要翻译：垂直功率MOSFET的导通电阻和漏电流将被减小。在具有纵向和横向地布置在半导体衬底的主表面上的单元MOSFET（单元）的垂直高击穿电压MOSFET中，单元被制成四边形形状，并且在每个单元中，其内端部暴露于四边形源接触孔的内部分别布置并对应于四边形的每一侧。每个源极区域是梯形的，并且梯形的下侧位于栅电极（栅极绝缘膜）的下方，而梯形的上侧部分暴露于源极接触孔的内部。四个源区域由四边形的对角区域彼此分开。

10. 发明申请

US20120012978A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120012978A1
公开(公告)日：2012-01-19
申请号：US13244133
申请日：2011-09-23
申请人： Kentaro OCHI , Akira Mishima , Takuro Kanazawa , Tetsuo Iijima , Katsuo Ishizaka , Norio Kido
发明人： Kentaro OCHI , Akira Mishima , Takuro Kanazawa , Tetsuo Iijima , Katsuo Ishizaka , Norio Kido
IPC分类号： H01L23/48
CPC分类号： H01L23/3107 , H01L23/49568 , H01L23/49575 , H01L24/33 , H01L25/115 , H01L2224/32245 , H01L2924/1301 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.
摘要翻译：提供了通过使用半导体封装形成的半导体器件。半导体器件包括在感应导体上相邻布置的两个半导体封装。两个半导体封装的端子由第三引线连接。第三引线被布置成基本上平行于感应导体。接头部分处的引线例如具有弯曲结构，并且第三引线布置成靠近感应导体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式