专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5117488A Microprogram controlled microprocessor having a selectively expandable instruction code length including independent description of operand addressing and a type of operation for an operand by single instruction in a common coding scheme 失效
标题翻译：具有可选择的可扩展指令码长度的微控制微控制器，其中包括独立的操作说明和通用编程方案中的单个操作的操作类型
公开(公告)号：US5117488A
公开(公告)日：1992-05-26
申请号：US265539
申请日：1988-11-01
申请人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
发明人： Kouki Noguchi , Fumio Tsuchiya , Takashi Tsukamoto , Shigeki Masumura , Hideo Nakamura , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F9/30178 , G06F9/261 , G06F9/30145 , G06F9/30156
摘要： In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

2. 发明授权

US5321845A Single-chip microcomputer including non-volatile memory elements 失效
标题翻译：单片机包括非易失性存储元件
公开(公告)号：US5321845A
公开(公告)日：1994-06-14
申请号：US94920
申请日：1993-07-22
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78 , G06F9/06
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
摘要翻译：内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

3. 发明授权

US5784637A Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip 失效
标题翻译：集成在半导体芯片上的单片半导体集成电路器件和微计算机
公开(公告)号：US5784637A
公开(公告)日：1998-07-21
申请号：US414157
申请日：1995-03-31
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78
CPC分类号： G06F9/24 , G06F15/7814
摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.
摘要翻译：形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线或输入/输出端口）和可变逻辑电路（或子处理器）。可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

4. 发明授权

US5428808A Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：US5428808A
公开(公告)日：1995-06-27
申请号：US217826
申请日：1994-03-25
申请人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
发明人： Terumi Sawase , Kouki Noguchi , Hideo Nakamura , Yasushi Akao , Shiro Baba , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F15/78 , G06F9/06
CPC分类号： G06F9/24 , G06F15/7814
摘要： A logic circuit built in a single-chip microprocessor is configured of electrically-programmable memory elements, and information is written into the memory elements from outside, whereby the logic circuit having any desired logical functions can be constructed. The writing operation of the memory elements can be executed in a short time, and a user can obtain the single-chip microprocessor having hardware of peculiar prescribed specifications, in a short period.
摘要翻译：内置在单芯片微处理器中的逻辑电路由电可编程存储器元件构成，并且信息从外部写入存储器元件，由此可以构建具有任何期望的逻辑功能的逻辑电路。可以在短时间内执行存储元件的写入操作，并且用户可以在短时间内获得具有特定规定规格的硬件的单片微处理器。

5. 发明授权

US5165086A Microprocessor chip using two-level metal lines technology 失效
标题翻译：微处理器芯片采用二级金属线技术
公开(公告)号：US5165086A
公开(公告)日：1992-11-17
申请号：US527866
申请日：1990-05-24
申请人： Shigehiro Kamejima , Yoshimune Hagiwara , Kouki Noguchi , Minoru Ishii , Tadahiko Nishimukai , Hideo Nakamura , Haruo Koizumi , Hiroyuki Masuda
发明人： Shigehiro Kamejima , Yoshimune Hagiwara , Kouki Noguchi , Minoru Ishii , Tadahiko Nishimukai , Hideo Nakamura , Haruo Koizumi , Hiroyuki Masuda
IPC分类号： H01L27/02
CPC分类号： H01L27/0207
摘要： A microprocessor chip including a ROM portion for storing a microprogram, an execution unit portion for executing an arithmetic operation and random logic circuits disposed between the ROM portion and the execution unit portion. Two-level metal lines technology is used for supplying power for grounding and for providing input/output interconnect lines for the random logic circuits.
摘要翻译：一种微处理器芯片，包括用于存储微程序的ROM部分，用于执行算术运算的执行单元部分和布置在ROM部分和执行单元部分之间的随机逻辑电路。两级金属线技术用于为接地提供电源，并为随机逻辑电路提供输入/输出互连线。

6. 发明授权

US4910466A Selecting means for selecting a plurality of information 失效
标题翻译：用于选择多个信息的选择装置
公开(公告)号：US4910466A
公开(公告)日：1990-03-20
申请号：US304878
申请日：1989-01-31
申请人： Atsushi Kiuchi , Jun Ishida , Kenji Kaneko , Tetsuya Nakagawa , Tomoru Sato , Shigeki Masumura , Noriyasu Suzuki , Yoshimune Hagiwara
发明人： Atsushi Kiuchi , Jun Ishida , Kenji Kaneko , Tetsuya Nakagawa , Tomoru Sato , Shigeki Masumura , Noriyasu Suzuki , Yoshimune Hagiwara
IPC分类号： H03K17/00 , H03K17/693
CPC分类号： H03K17/693
摘要： A plurality of external input information are added to a selecting circuit. The output of the selecting circuit is fed back as one of the external input information to the selecting circuit. The input signal groups are decoded, and are produced as control signals to specify the external input information in synchronism with clock signals. When the input select signal groups have the non-selection mode, the output that is fed back is necessarily selected.
摘要翻译：多个外部输入信息被添加到选择电路。选择电路的输出作为外部输入信息之一反馈给选择电路。输入信号组被解码，并作为控制信号产生，以便与时钟信号同步地指定外部输入信息。当输入选择信号组具有非选择模式时，必须选择反馈的输出。

7. 发明授权

US5109492A Microprocessor which terminates bus cycle when access address falls within a predetermined processor system address space 失效
标题翻译：当访问地址落在预定的处理器系统地址空间内时终止总线周期的微处理器
公开(公告)号：US5109492A
公开(公告)日：1992-04-28
申请号：US84808
申请日：1987-08-13
申请人： Kouki Noguchi , Yoshimune Hagiwara , Kazuhiko Iwasaki , Hirokazu Aoki , Shigeru Shimada
发明人： Kouki Noguchi , Yoshimune Hagiwara , Kazuhiko Iwasaki , Hirokazu Aoki , Shigeru Shimada
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/4208 , G06F13/36
摘要： A microprocessor suitable for a high speed processor system prevents extension of a bus cycle due to delay of generation of a bus cycle end signal and effectively utilizes a characteristic of a high speed accessable external device.
摘要翻译：适用于高速处理器系统的微处理器防止由于总线周期结束信号的产生的延迟而导致总线周期的扩展，并且有效地利用高速可访问的外部设备的特性。

8. 发明授权

US5511211A Method for flexibly developing a data processing system comprising rewriting instructions in non-volatile memory elements after function check indicates failure of required functions 失效
标题翻译：用于灵活地开发数据处理系统的方法，包括在功能检查之后重写非易失性存储器元件中的指令，指示所需功能的失败
公开(公告)号：US5511211A
公开(公告)日：1996-04-23
申请号：US102156
申请日：1993-08-04
申请人： Yasushi Akao , Shiro Baba , Terumi Sawase , Yoshimune Hagiwara
发明人： Yasushi Akao , Shiro Baba , Terumi Sawase , Yoshimune Hagiwara
IPC分类号： G06F9/24 , G06F9/445 , G06F15/78 , G06F9/312 , G06F13/40 , G06F15/20
CPC分类号： G06F8/60 , G06F15/7814 , G06F9/24
摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.
摘要翻译：在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据将系统的所需规格和功能写入逻辑功能块。由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。

9. 发明授权

US5426744A Single chip microprocessor for satisfying requirement specification of users 失效
标题翻译：单芯片微处理器，用于满足用户的要求规格
公开(公告)号：US5426744A
公开(公告)日：1995-06-20
申请号：US203761
申请日：1994-03-01
申请人： Terumi Sawase , Yoshimune Hagiwara , Hideo Nakamura , Hiroyuki Hatori , Shirou Baba , Yasushi Akao
发明人： Terumi Sawase , Yoshimune Hagiwara , Hideo Nakamura , Hiroyuki Hatori , Shirou Baba , Yasushi Akao
IPC分类号： G06F9/24 , G06F9/38 , G06F11/267 , G06F15/78 , G06F9/26
CPC分类号： G06F9/3879 , G06F11/2236 , G06F15/7814 , G06F15/7867 , G06F9/24 , G06F9/3897
摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.
摘要翻译：本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。可以通过任意形成的逻辑功能来满足各种用户的需求规格。

10. 发明授权

US4996659A Method of diagnosing integrated logic circuit 失效
标题翻译：诊断集成逻辑电路的方法
公开(公告)号：US4996659A
公开(公告)日：1991-02-26
申请号：US84153
申请日：1987-08-12
申请人： Noboru Yamaguchi , Hideo Nakamura , Yoshimune Hagiwara , Tsukasa Sato , Haruo Koizumi
发明人： Noboru Yamaguchi , Hideo Nakamura , Yoshimune Hagiwara , Tsukasa Sato , Haruo Koizumi
IPC分类号： G01R31/305 , G01R31/3193
CPC分类号： G01R31/3193 , G01R31/305
摘要： A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.
摘要翻译：一种诊断具有功能块的集成逻辑电路的方法，其中测试信号被提供给逻辑电路; 通过使用诸如电子束探测装置或激光束探测装置的非接触探测装置来检测来自至少一个功能块的输入信号和输出信号; 利用检测到的输入信号对功能块的正常逻辑运算进行仿真，以提供模拟输出信号; 检测和模拟的输出信号相互比较; 并且根据比较的结果将功能块确定为正常或异常。当功能块包括多个逻辑元件时，通过非接触探测装置检测功能元件的输出，将检测到的输出与对应的模拟输出进行比较并重复检测，可以将异常的原因追溯到故障功能元件并比较功能块中的其他功能元素，直到比较结果重合。将作为比较结果提供一致的信号的功能元件确定为故障功能元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式