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1. 发明授权

US5946963A Bevel gear hot-forging apparatus 失效
标题翻译：锥齿轮热锻设备
公开(公告)号：US5946963A
公开(公告)日：1999-09-07
申请号：US101469
申请日：1998-07-10
申请人： Kouji Suzuki , Akihiko Minowa , Shuichi Yamane , Hiroshi Sugita , Seishi Okada , Takashi Asada
发明人： Kouji Suzuki , Akihiko Minowa , Shuichi Yamane , Hiroshi Sugita , Seishi Okada , Takashi Asada
IPC分类号： B21J5/02 , B21J5/12 , B21J13/02 , B21J13/12 , B21J13/14 , B21K1/30 , B21K27/00
CPC分类号： B21K1/305 , B21K1/30 , Y10T29/49474
摘要： At the time of closing a die mold, an upper die (18) is rotated with respect to screws (44a-44d) while being brought into contact with a lower die (14) by means of drive gears (42a-42d) and a driven gear (40), wherein a closing force is applied to the material (W) by plate springs (60). Subsequently, at the time of opening the die, under an opposite operation, the upper die (18) is opened while being simultaneously rotated with respect to the screws (44a-44d) which are supported by coil springs (54a-54d), whereby a spiral bevel gear (72) is released from the mold. Accordingly, at the time of die closing, the closing force is kept stable, whereas when the die is opened, imposition of a large force to the gear teeth is prevented, so that bevel gears (72) of high quality and high yield rate can be produced.
摘要翻译： PCT No.PCT / JP97 / 04087第 371日期：1998年7月10日 102（e）1998年7月10日PCT 1997年11月10日PCT PCT。出版物WO98 / 20994 日期1998年5月22日在关闭模具的时候，上模18相对于螺钉（44a-44d）旋转，同时通过驱动齿轮（42a-44d）与下模（14）接触， 42d）和从动齿轮（40），其中通过板簧（60）向材料（W）施加闭合力。随后，在打开模具时，在相反的操作下，上模18被打开，同时相对于由螺旋弹簧（54a-54d）支撑的螺钉（44a-44d）同时旋转，由此螺旋伞齿轮（72）从模具中释放出来。因此，在闭合时，闭合力保持稳定，而当模具打开时，可以防止对齿轮齿施加大的力，使得高质量和高产率的锥齿轮（72）可以生产。

2. 发明申请

US20130159638A1 INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS METHOD 审中-公开
标题翻译：信息处理设备和存储器访问方法
公开(公告)号：US20130159638A1
公开(公告)日：2013-06-20
申请号：US13608681
申请日：2012-09-10
申请人： Hideyuki Koinuma , Seishi Okada , Go Sugizaki
发明人： Hideyuki Koinuma , Seishi Okada , Go Sugizaki
IPC分类号： G06F13/00
CPC分类号： G06F12/0284 , G06F12/1072 , G06F12/1441 , G06F2212/2542
摘要： A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit.
摘要翻译：节点包括执行逻辑地址和物理地址之间的转换的第一转换单元。节点包括第二转换单元，其执行用于识别包括在多个节点中的每个节点中的处理器的物理地址和处理器标识信息之间的转换。节点包括发送单元，发送包括用于访问由物理地址指示的存储区域的物理地址和处理器识别信息的发送数据。该节点包括本地确定单元，该本地确定单元基于由所接收的发送数据中包含的物理地址来确定由从另一节点接收的发送数据指示的接入是对本地区域的访问还是对共享区域的访问接收单元。

3. 发明申请

US20060212683A1 Information processing system, pipeline processor, and computer readable recording medium in which busy judgment program is stored 失效
标题翻译：信息处理系统，流水线处理器和存储有忙碌判断程序的计算机可读记录介质
公开(公告)号：US20060212683A1
公开(公告)日：2006-09-21
申请号：US11157809
申请日：2005-06-22
申请人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
发明人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
IPC分类号： G06F15/00
CPC分类号： G06F9/3824
摘要： In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.
摘要翻译：在本发明中，为了能够毫不费力地进行寄存器的繁忙判断，并且在不增加用于将请求存储到流水线寄存器最后一级提供的寄存器中的硬件资源数量的请求在流水线处理器中的流水线寄存器的中途保留一个第一计数器，用于对插入在流水线寄存器中的判断部分之间的寄存器中的有效请求数进行计数，以及判断请求是否为有效请求和请求队列的第一计数器提供用于基于第一计数器计数的有效请求的数量来判断请求队列是否处于忙状态的忙判断部分，并且由判断部分根据忙碌判断的忙碌状态判断结果进行判断部分。

4. 发明授权

US4933841A Microcode reading control system 失效
标题翻译：微码阅读控制系统
公开(公告)号：US4933841A
公开(公告)日：1990-06-12
申请号：US204749
申请日：1988-06-10
申请人： Tsuyoshi Mori , Seishi Okada
发明人： Tsuyoshi Mori , Seishi Okada
IPC分类号： G03B17/02 , G03B7/26 , G03B17/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/38
CPC分类号： G06F9/267 , G06F9/28
摘要： A microcode reading control system in an information processing system wherein a machine instruction is divided into microcode instructions as a plurality of steps, each step is further divided into a plurality of stages, and the stages of the microcode instructions are processed in parallel with advanced retrieval control, a first aspect of which provides duplexed control storages storing the microcode instructions read in at a first step of the machine instruction, one of the control storages being read only at the first step of a branch target machine instruction of a branch machine instruction, and a second aspect of which provides a first control storage storing microcode instructions to control the first steps of the machine instructions and a second control storage storing microcode instruction to control the second steps and thereafter of the machine instructions, the first control storage reading the stored microcode instruction at the second stage of the first step of the machine instruction, and the second control storage reading at the first stage of the second step and thereafter of the machine instructions. Thus, in a processing of the branch machine instruction, the control can be accelerated.
摘要翻译：一种信息处理设备中的微代码读取控制系统，其中机器指令被分为微代码作为多个步骤，每个步骤进一步分为多个级，并且微程序的级与高级控制并行处理，其第一方面提供存储在机器指令的第一步骤中读取的微代码的双工控制存储器，其中一个控制存储器仅在分支指令的分支目标指令的第一步读取，并且其第二方面提供存储用于控制机器指令的第一步骤的微码的第一控制存储器和存储微码的第二控制存储器，以控制第二步骤和之后的机器指令，第一控制存储器在第一步骤的第二阶段读取存储的微代码以及在第二步骤a的第一阶段的第二控制存储读取 d之后的机器指令。因此，在分支指令的处理中，可以加速先前的控制。

5. 发明授权

US07783840B2 Method and apparatus for controlling memory system 有权
标题翻译：用于控制存储器系统的方法和装置
公开(公告)号：US07783840B2
公开(公告)日：2010-08-24
申请号：US10999972
申请日：2004-12-01
申请人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
发明人： Makoto Hataida , Takao Matsui , Daisuke Itoh , Seishi Okada , Takaharu Ishizuka
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0817 , G06F2212/507
摘要： A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.
摘要翻译：高速缓存状态维持单元存储存储在高速缓冲存储器的每个条目中的数据的地址信息，并将每个条目的状态保持为“强修改”，“弱修改”，“共享”和“无效”中的任何一个。数据获取过程选择单元在接收到数据读取请求时，基于地址信息和状态来选择至少一个数据获取过程。读取数据传送单元从获取的数据中选择最新数据，并将最新数据传送到发出数据读取请求的处理器。缓存状态更新单元在注册数据的地址信息时根据数据读取请求的类型来更新条目的状态。

6. 发明授权

US07502956B2 Information processing apparatus and error detecting method 有权
标题翻译：信息处理装置和误差检测方法
公开(公告)号：US07502956B2
公开(公告)日：2009-03-10
申请号：US10985042
申请日：2004-11-10
申请人： Jin Takahashi , Seishi Okada
发明人： Jin Takahashi , Seishi Okada
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0793
摘要： An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error occurrence to at least one of the computing units that includes the recording unit when an error occurs in the each of the computing units itself.
摘要翻译：信息处理装置包括多个计算单元。计算单元中的至少一个包括记录单元，其记录每个计算单元中的错误发生的状态。每个计算单元包括错误通知单元，当在每个计算单元本身中发生错误时，将错误发生通知给包括记录单元的至少一个计算单元。

7. 发明授权

US07490219B2 Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors 失效
标题翻译：计数器根据具有多个流水线处理器的系统中的判断计数有效请求
公开(公告)号：US07490219B2
公开(公告)日：2009-02-10
申请号：US11157809
申请日：2005-06-22
申请人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
发明人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
IPC分类号： G06F15/00 , G06F15/76 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3824
摘要： In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.
摘要翻译：在本发明中，为了能够毫不费力地进行寄存器的繁忙判断，并且在不增加用于将请求存储到流水线寄存器最后一级提供的寄存器中的硬件资源数量的请求在流水线处理器中的流水线寄存器的中途保留一个第一计数器，用于对插入在流水线寄存器中的判断部分之间的寄存器中的有效请求数进行计数，以及判断请求是否为有效请求和请求队列的第一计数器，以及提供用于基于第一计数器计数的有效请求的数量来判断请求队列是否处于忙状态的忙判断部分，并且由判断部分根据忙碌判断的忙碌状态判断结果进行判断部分。

8. 发明授权

US5197145A Buffer storage system using parallel buffer storage units and move-out buffer registers 失效
标题翻译：使用平行缓冲存储单元和移出缓冲区寄存器的缓冲存储系统
公开(公告)号：US5197145A
公开(公告)日：1993-03-23
申请号：US409711
申请日：1989-09-20
申请人： Yoshimoto Kitamura , Seishi Okada
发明人： Yoshimoto Kitamura , Seishi Okada
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0846
摘要： A buffer storage system provided between an instruction executing portion and a main storage for enabling the instruction executing portion to quickly fetch and store date in a frequently-accessed address area. The buffer storage system includes a plurality of buffer storages each storing the same data; and a move-out buffer register provided between the plurality of buffer storages and the main storage. When data held in the buffer storages is required to be moved out to the main storage, a part of the data to be moved out is transferred from each of the plurality of buffer storages to a corresponding portion of the move-out buffer register, and then the data is transferred from the move-out buffer register to the main storage. The transferring of the parts of the data from the plurality of buffer storages to the corresponding portions of the move-out buffer register are concurrently carried out, and the parts of the data concurrently transferred from all of the buffer storages to the move-out buffer register constitute the whole of the data to be moved out.

9. 发明授权

US09003082B2 Information processing apparatus, arithmetic device, and information transferring method 有权
标题翻译：信息处理装置，运算装置和信息传送方法
公开(公告)号：US09003082B2
公开(公告)日：2015-04-07
申请号：US13599114
申请日：2012-08-30
申请人： Seishi Okada , Toshikazu Ueki , Hideyuki Koinuma
发明人： Seishi Okada , Toshikazu Ueki , Hideyuki Koinuma
IPC分类号： G06F5/00 , G06F9/54
CPC分类号： G06F9/546
摘要： An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.
摘要翻译：一种包括多个节点的信息处理装置。每个节点包括处理器，存储设备和存储单元，其中存储有多个指针集合，每个指针集合中指示当从另一个节点接收的数据存储在存储设备中时使用的地址的写指针与读取指针，指示当从存储设备读取数据时使用的地址。每个节点包括通知单元，该通知单元通知与指示符集合的指针标识符的数据的发送源相对应的节点。每个节点包括保持单元，该保持单元根据由指针标识符指示的指针集中的写指针指示的地址将接收到的数据保存在存储设备中。

10. 发明授权

US08723702B2 Data transfer method, and code conversion circuit and apparatus 失效
标题翻译：数据传输方法及代码转换电路及装置
公开(公告)号：US08723702B2
公开(公告)日：2014-05-13
申请号：US13312462
申请日：2011-12-06
申请人： Seishi Okada
发明人： Seishi Okada
IPC分类号： H03M5/00
CPC分类号： H03M7/14
摘要： A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.
摘要翻译：数据传送方法复用具有位宽M（M是大于或等于3的自然数）的数据字符和具有位宽N（N是大于或等于1的自然数）的控制字符，并且添加指示控制字符是否有效的控制字符有效信号，以便产生具有位宽M + 1或N + 3的符号代码（以较大者为准），并将符号代码从并行数据转换为串行数据为输出到传输线。

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