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1. 发明申请

US20110320901A1 DATA TRANSFER DEVICE AND CONTROL METHOD OF DATA TRANSFER DEVICE 有权
标题翻译：数据传输设备和数据传输设备的控制方法
公开(公告)号：US20110320901A1
公开(公告)日：2011-12-29
申请号：US13227852
申请日：2011-09-08
申请人： Kenta SATO , Takashi Yamamoto , Toshikazu Ueki , Yuka Hosokawa
发明人： Kenta SATO , Takashi Yamamoto , Toshikazu Ueki , Yuka Hosokawa
IPC分类号： H04L1/08 , G06F11/14
CPC分类号： H04L1/00 , H03M13/09 , H04L1/0061 , H04L1/1829 , H04L1/1835 , H04L1/242
摘要： A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted.
摘要翻译：数据传送装置包括数据发送电路，包括产生用于检测数据中的错误的错误检测码的错误检测码生成单元，以及发送数据和错误检测码的发送单元以及表示相应数据的再发送使能信息数据接收电路包括接收发送数据的接收单元，所发送的错误检测码和所发送的重传使能信息，错误检测单元，基于接收到的数据，基于误差检测码，当接收单元接收到重传使能信息时保持检测到错误的数据的误差数据保持单元;以及误差数据比较单元，其将保留在误差数据保持单元中的错误检测数据与相应的重发数据

2. 发明申请

US20110107157A1 REGISTER ACCESS CONTROL METHOD AND CIRCUIT 审中-公开
标题翻译：寄存器访问控制方法和电路
公开(公告)号：US20110107157A1
公开(公告)日：2011-05-05
申请号：US12915555
申请日：2010-10-29
申请人： Akira OKAMOTO , Seiji Satta , Toshikazu Ueki , Takashi Yamamoto
发明人： Akira OKAMOTO , Seiji Satta , Toshikazu Ueki , Takashi Yamamoto
IPC分类号： G06F12/00 , G06F11/07
CPC分类号： G06F11/0751 , G06F11/0724
摘要： A register access control circuit and method includes extracting data written to a plurality of registers by specifying the common address in response to read access to a common address, comparing the data extracted from the respective registers, and outputting the data extracted from one of the registers as read data when the data extracted from the respective registers match.
摘要翻译：一种寄存器访问控制电路和方法，包括：响应于对公共地址的读取访问指定公共地址，提取写入多个寄存器的数据，比较从各个寄存器提取的数据，并输出从寄存器之一提取的数据作为从各个寄存器提取的数据匹配时的读取数据。

3. 发明申请

US20100228507A1 TRACE DEVICE AND TRACE METHOD FOR FAILURE ANALYSIS 审中-公开
标题翻译：用于故障分析的跟踪设备和跟踪方法
公开(公告)号：US20100228507A1
公开(公告)日：2010-09-09
申请号：US12714939
申请日：2010-03-01
申请人： Yuka HOSOKAWA , Takashi Yamamoto , Toshikazu Ueki , Kenta Sato
发明人： Yuka HOSOKAWA , Takashi Yamamoto , Toshikazu Ueki , Kenta Sato
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G01R31/31705
摘要： A trace device for tracing data in an LSI includes a trace data storing unit that stores trace data, a trace target determination unit that determines whether to store trace data of one of a plurality of trace targets in the trace data storing unit based on an operating state of a system including the LSI and based on a failure occurrence report reported from any of the trace targets in response to an occurrence of an error in the trace target residing in the LSI and a trace target selection unit that selects the trace data to be stored in the trace data storing unit out of the trace data from the plurality of trace targets based on the determining by the trace target determination unit, and stores the selected trace data in the trace data storing unit.
摘要翻译：用于在LSI中跟踪数据的跟踪装置包括存储跟踪数据的跟踪数据存储单元，跟踪目标确定单元，其基于操作确定是否将多个跟踪目标中的一个跟踪数据存储在跟踪数据存储单元中包括LSI的系统的状态，并且基于从任何跟踪目标报告的响应于驻留在LSI中的跟踪目标中的错误的发生的故障发生报告和选择跟踪数据的跟踪目标选择单元基于轨迹目标确定单元的确定，从多个跟踪目标中的跟踪数据中存储在跟踪数据存储单元中，并将所选择的跟踪数据存储在跟踪数据存储单元中。

4. 发明申请

US20100191942A1 Information processor and control method 失效
标题翻译：信息处理器和控制方法
公开(公告)号：US20100191942A1
公开(公告)日：2010-07-29
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

5. 发明申请

US20080046695A1 System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function 有权
标题翻译：系统控制器，相同地址请求排队防止方法和具有相同地址请求排队防止功能的信息处理装置
公开(公告)号：US20080046695A1
公开(公告)日：2008-02-21
申请号：US11790266
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F9/30 , G06F12/00
CPC分类号： G06F13/1642
摘要： In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.
摘要翻译：在包括CPU发出的请求队列的系统控制器中，具有处理具有相同地址的多个请求的电路不被输入到CPU发出的请求队列，除了高速缓存替换请求以外的最新请求被保留部分。因此，即使发出的请求高速缓存替换请求的地址与CPU发出的请求队列所保留的请求的地址相匹配，也不会重新发出对高速缓存替换请求的发出请求，而是在CPU发出的请求队列中排队当发出的缓存替换请求的地址与输入请求保留部分保留的整个地址不匹配时。

6. 发明申请

US20080046663A1 System controller, snoop tag modification method and information processing apparatus having snoop tag modificaton function 有权
标题翻译：系统控制器，snoop标签修改方法和具有snoop标签修改功能的信息处理设备
公开(公告)号：US20080046663A1
公开(公告)日：2008-02-21
申请号：US11790263
申请日：2007-04-24
申请人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
发明人： Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Takashi Yamamoto , Yuka Hosokawa , Takeshi Owaki , Daisuke Itou
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.
摘要翻译：在多处理器系统中，系统控制器包括窥探标签，这些标签是由各个CPU保留的缓存标签上的复制信息。如果在连接到同一CPU总线的每个CPU的缓存标签中的S（共享状态）中登记相同的地址，则只在与CPU对应的任何一个snoop标签中的S（共享状态）中注册该地址其中注册了相同的地址。

7. 发明申请

US20060212683A1 Information processing system, pipeline processor, and computer readable recording medium in which busy judgment program is stored 失效
标题翻译：信息处理系统，流水线处理器和存储有忙碌判断程序的计算机可读记录介质
公开(公告)号：US20060212683A1
公开(公告)日：2006-09-21
申请号：US11157809
申请日：2005-06-22
申请人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
发明人： Takao Matsui , Yuka Hosokawa , Makoto Hataida , Toshikazu Ueki , Seishi Okada
IPC分类号： G06F15/00
CPC分类号： G06F9/3824
摘要： In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.
摘要翻译：在本发明中，为了能够毫不费力地进行寄存器的繁忙判断，并且在不增加用于将请求存储到流水线寄存器最后一级提供的寄存器中的硬件资源数量的请求在流水线处理器中的流水线寄存器的中途保留一个第一计数器，用于对插入在流水线寄存器中的判断部分之间的寄存器中的有效请求数进行计数，以及判断请求是否为有效请求和请求队列的第一计数器提供用于基于第一计数器计数的有效请求的数量来判断请求队列是否处于忙状态的忙判断部分，并且由判断部分根据忙碌判断的忙碌状态判断结果进行判断部分。

8. 发明申请

US20060212656A1 Dual storage apparatus and control method for the dual storage apparatus 有权
标题翻译：双存储设备的双存储设备和控制方法
公开(公告)号：US20060212656A1
公开(公告)日：2006-09-21
申请号：US11237934
申请日：2005-09-29
申请人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
发明人： Toshikazu Ueki , Takaharu Ishizuka , Takao Matsui , Makoto Hataida , Yuka Hosokawa
IPC分类号： G06F12/00
CPC分类号： G06F11/1008 , G06F11/1666 , G06F11/20 , G11C5/005
摘要： A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.
摘要翻译：提供了一种双存储装置，其包括用于分别保存一组相同数据的第一和第二存储器，以及用于选择从第一和第二存储器分别读取的两（2）组数据中的任何一个基于读取控制信号输入到选择器中，具有请求管理单元，当输入了读取控制信号时，将用于识别读取控制信号的标识符附加到所输入的读取控制信号并输出该信号和标识符; 以及用于第一和第二存储器中的每一个的多个存储器控制单元。双存储装置通过验证由请求管理单元附加的标识符的一致性来检测同步错误，并且控制选择器使得来自未检测到同步错误的系统的数据。

9. 发明授权

US09003082B2 Information processing apparatus, arithmetic device, and information transferring method 有权
标题翻译：信息处理装置，运算装置和信息传送方法
公开(公告)号：US09003082B2
公开(公告)日：2015-04-07
申请号：US13599114
申请日：2012-08-30
申请人： Seishi Okada , Toshikazu Ueki , Hideyuki Koinuma
发明人： Seishi Okada , Toshikazu Ueki , Hideyuki Koinuma
IPC分类号： G06F5/00 , G06F9/54
CPC分类号： G06F9/546
摘要： An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.
摘要翻译：一种包括多个节点的信息处理装置。每个节点包括处理器，存储设备和存储单元，其中存储有多个指针集合，每个指针集合中指示当从另一个节点接收的数据存储在存储设备中时使用的地址的写指针与读取指针，指示当从存储设备读取数据时使用的地址。每个节点包括通知单元，该通知单元通知与指示符集合的指针标识符的数据的发送源相对应的节点。每个节点包括保持单元，该保持单元根据由指针标识符指示的指针集中的写指针指示的地址将接收到的数据保存在存储设备中。

10. 发明授权

US08806291B2 Data transfer device and control method of data transfer device 有权
标题翻译：数据传输装置及数据传输装置的控制方法
公开(公告)号：US08806291B2
公开(公告)日：2014-08-12
申请号：US13227852
申请日：2011-09-08
申请人： Kenta Sato , Takashi Yamamoto , Toshikazu Ueki , Yuka Hosokawa
发明人： Kenta Sato , Takashi Yamamoto , Toshikazu Ueki , Yuka Hosokawa
IPC分类号： H03M13/00 , H04L1/18 , H04L1/00
CPC分类号： H04L1/00 , H03M13/09 , H04L1/0061 , H04L1/1829 , H04L1/1835 , H04L1/242
摘要： A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted.
摘要翻译：数据传送装置包括数据发送电路，包括产生用于检测数据中的错误的错误检测码的错误检测码生成单元，以及发送数据和错误检测码的发送单元以及表示相应数据的再发送使能信息数据接收电路包括接收发送数据的接收单元，所发送的错误检测码和所发送的重传使能信息，错误检测单元，基于接收到的数据，基于误差检测码，当接收单元接收到重传使能信息时保持检测到错误的数据的误差数据保持单元;以及误差数据比较单元，其将保留在误差数据保持单元中的错误检测数据与相应的重发数据

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