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1. 发明授权

US07502956B2 Information processing apparatus and error detecting method 有权
标题翻译：信息处理装置和误差检测方法
公开(公告)号：US07502956B2
公开(公告)日：2009-03-10
申请号：US10985042
申请日：2004-11-10
申请人： Jin Takahashi , Seishi Okada
发明人： Jin Takahashi , Seishi Okada
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0793
摘要： An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error occurrence to at least one of the computing units that includes the recording unit when an error occurs in the each of the computing units itself.
摘要翻译：信息处理装置包括多个计算单元。计算单元中的至少一个包括记录单元，其记录每个计算单元中的错误发生的状态。每个计算单元包括错误通知单元，当在每个计算单元本身中发生错误时，将错误发生通知给包括记录单元的至少一个计算单元。

2. 发明申请

US20060020851A1 Information processing apparatus and error detecting method 有权
公开(公告)号：US20060020851A1
公开(公告)日：2006-01-26
申请号：US10985042
申请日：2004-11-10
申请人： Jin Takahashi , Seishi Okada
发明人： Jin Takahashi , Seishi Okada
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/0793
摘要： An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error occurrence to at least one of the computing units that includes the recording unit when an error occurs in the each of the computing units itself.

3. 发明授权

US07584388B2 Error notification method and information processing apparatus 失效
标题翻译：错误通知方法和信息处理装置
公开(公告)号：US07584388B2
公开(公告)日：2009-09-01
申请号：US11182848
申请日：2005-07-18
申请人： Jin Takahashi
发明人： Jin Takahashi
IPC分类号： G06F11/00
CPC分类号： G06F11/0772
摘要： An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system in a mirror mode. The error notification method generates an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels, reduces the error level of a corresponding error interrupt signal when the error within the first processor system is avoided in the mirror mode, and notifies the error to each processor within the first and second processor systems using the error interrupt signal.
摘要翻译：一种错误通知方法将在第一和第二处理器系统中产生的错误通知给第一和第二处理器系统内的每个处理器，该计算机系统包括可在正常模式下操作的第一处理器系统，第二处理器系统与第一处理器系统以镜像模式。错误通知方法产生一个错误中断信号，该错误中断信号通过多个错误级别中的相应的一个指示每个错误，当在镜像模式中避免第一处理器系统内的错误时，降低对应的错误中断信号的错误电平，以及使用错误中断信号将错误通知给第一和第二处理器系统内的每个处理器。

4. 发明申请

US20060023825A1 Device and method for synchronous data transmission using reference signal 有权
标题翻译：使用参考信号同步数据传输的装置和方法
公开(公告)号：US20060023825A1
公开(公告)日：2006-02-02
申请号：US11057146
申请日：2005-02-15
申请人： Shinya Kato , Takayoshi Kyono , Ryuichi Nisiyama , Jin Takahashi
发明人： Shinya Kato , Takayoshi Kyono , Ryuichi Nisiyama , Jin Takahashi
IPC分类号： H04L25/00
CPC分类号： H04L7/0331 , G06F13/4273 , H04L7/005 , H04L25/14
摘要： A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.
摘要翻译：数据发送器和数据接收器从公共参考信号产生相应的同步信号。数据接收器使用每个由接收到的并行数据的单个比特构成的1比特数据信号中的每一个来调整第一时钟信号的相位，从而确保每一比特数据信号的建立时间和保持时间并根据调整后的时钟信号将每一位数据信号加载到数据缓冲器中。然后，数据接收机根据第二时钟信号并与接收机同步信号同步地读取保存在数据缓冲器中的数据。当检测到与发射机同步信号同步发送的训练模式时，初始化要加载数据信号的存储器位置。

5. 发明申请

US20100153663A1 MEMORY ACCESS SYSTEM AND METHOD 审中-公开
标题翻译：存储器访问系统和方法
公开(公告)号：US20100153663A1
公开(公告)日：2010-06-17
申请号：US12711454
申请日：2010-02-24
申请人： Fumitake Sugano , Jin Takahashi
发明人： Fumitake Sugano , Jin Takahashi
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F12/00 , G06F13/1684
摘要： A memory access system has a first memory for storing data, a second memory for storing data, a processor for processing data, the processor including a first memory controller for reading out data from or writing data into the first memory, a second memory controller connected to the processor, for reading out data from or writing data into the first memory and the second memory, and a selector for selecting either the first memory controller or the second memory controller, and enabling either the first and the second memory controllers to read out data from or write data into the first memory.
摘要翻译：存储器访问系统具有用于存储数据的第一存储器，用于存储数据的第二存储器，用于处理数据的处理器，所述处理器包括用于从第一存储器读出数据或将数据写入数据的第一存储器控制器，第二存储器控制器连接用于从第一存储器和第二存储器读出数据或将数据写入第一存储器和第二存储器;以及选择器，用于选择第一存储器控制器或第二存储器控制器，以及使得第一和第二存储器控制器能够读出将数据从或将数据写入第一存储器。

6. 发明申请

US20050224310A1 Method for optimizing groove structure of friction plate of wet type friction engagement apparatus 失效
标题翻译：湿式摩擦接合装置摩擦片槽结构优化方法
公开(公告)号：US20050224310A1
公开(公告)日：2005-10-13
申请号：US11062107
申请日：2005-02-18
申请人： Chen Li , Jin Takahashi
发明人： Chen Li , Jin Takahashi
IPC分类号： F16D13/64 , F16D13/74 , F16D65/12 , F16D69/00
CPC分类号： F16D65/12 , F16D13/64 , F16D13/648 , F16D13/74 , F16D2069/004
摘要： The object of the present invention is to provide an optimizing method for a groove structure of a friction disk of a wet-type friction engaging element, which can reduce drag torque by increasing outgoing flow of lubricating oil on the friction surface and increasing the content of air in the lubricating oil. The optimizing method for a groove structure of a friction disk of a wet-type friction engagement element comprising a sectoral inner section 12 of a groove 10 widening inwardly formed on the surface of a friction member of the wet-type friction engaging element, wherein the outgoing flow per groove area is calculated based on the entrance angle (opening angle) θ of the inner section 12 and the ratio h/w of the full length w of the groove 10 to the length h of the inner section; and then a range of the entrance angle (opening angle) θ of the inner section and the ratio h/w of the full length w of the groove to the length h of the inner section is determined where the outgoing flow per groove area is at least a certain value.
摘要翻译：本发明的目的是提供一种用于湿式摩擦接合元件的摩擦盘的槽结构的优化方法，其可以通过增加摩擦表面上的润滑油的流出量来增加阻力矩，并且增加其含量润滑油中的空气。湿式摩擦接合元件的摩擦盘的槽结构的优化方法包括在湿式摩擦接合元件的摩擦构件的表面上向内扩大的槽10的扇形内部部分12，其中，基于内部部分12的入射角（开口角）θ和凹槽10的全长w的比率h / w与内部部分的长度h计算出每个凹槽面积的流出量; 然后确定内部部分的入口角（开口角）θ以及槽的全长w与内部部分的长度h之比h / w的范围，其中每个沟槽区域的流出处于至少一定价值。

7. 发明授权

US08423699B2 Information processing apparatus and method for controlling information processing apparatus 失效
标题翻译：信息处理装置及信息处理装置的控制方法
公开(公告)号：US08423699B2
公开(公告)日：2013-04-16
申请号：US12929718
申请日：2011-02-10
申请人： Jin Takahashi
发明人： Jin Takahashi
IPC分类号： G06F13/00
CPC分类号： G06F13/38 , G06F11/00
摘要： According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.
摘要翻译：根据本实施例的一个方面，系统控制装置包括控制信号发送单元，其通过第一信号线向控制电路发送控制信号。控制信号包括用于对除了自己的控制电路以外的其他控制电路或对所有控制电路执行控制设置的命令。每个控制电路包括信号接收单元，其经由第一信号线接收从控制信号发送单元发送的控制信号;信号传送单元，其经由第二信号线将包含在接收到的控制信号中的命令传送到控制电路;以及控制设定单元，其根据接收到的控制信号中包含的命令或从其自身的控制电路以外的其他控制电路传送的命令，对自身的控制电路进行控制设定。

8. 发明申请

US20110145455A1 Information processing apparatus and method for controlling information processing apparatus 失效
标题翻译：信息处理装置及信息处理装置的控制方法
公开(公告)号：US20110145455A1
公开(公告)日：2011-06-16
申请号：US12929718
申请日：2011-02-10
申请人： Jin Takahashi
发明人： Jin Takahashi
IPC分类号： G06F13/38
CPC分类号： G06F13/38 , G06F11/00
摘要： According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.
摘要翻译：根据本实施例的一个方面，系统控制装置包括控制信号发送单元，其通过第一信号线向控制电路发送控制信号。控制信号包括用于对除了自己的控制电路以外的其他控制电路或对所有控制电路执行控制设置的命令。每个控制电路包括信号接收单元，其经由第一信号线接收从控制信号发送单元发送的控制信号;信号传送单元，其经由第二信号线将包含在接收到的控制信号中的命令传送到控制电路;以及控制设定单元，其根据接收到的控制信号中包含的命令或从其自身的控制电路以外的其他控制电路传送的命令，对自身的控制电路进行控制设定。

9. 发明授权

US07460630B2 Device and method for synchronous data transmission using reference signal 有权
标题翻译：使用参考信号同步数据传输的装置和方法
公开(公告)号：US07460630B2
公开(公告)日：2008-12-02
申请号：US11057146
申请日：2005-02-15
申请人： Shinya Kato , Takayoshi Kyono , Ryuichi Nisiyama , Jin Takahashi
发明人： Shinya Kato , Takayoshi Kyono , Ryuichi Nisiyama , Jin Takahashi
IPC分类号： H04L7/027
CPC分类号： H04L7/0331 , G06F13/4273 , H04L7/005 , H04L25/14
摘要： A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.
摘要翻译：数据发送器和数据接收器从公共参考信号产生相应的同步信号。数据接收器使用每个由接收到的并行数据的单个比特构成的1比特数据信号中的每一个来调整第一时钟信号的相位，从而确保每一比特数据信号的建立时间和保持时间并根据调整后的时钟信号将每一位数据信号加载到数据缓冲器中。然后，数据接收机根据第二时钟信号并与接收机同步信号同步地读取保存在数据缓冲器中的数据。当检测到与发射机同步信号同步发送的训练模式时，初始化要加载数据信号的存储器位置。

10. 发明申请

US20060212763A1 Error notification method and information processing apparatus 失效
公开(公告)号：US20060212763A1
公开(公告)日：2006-09-21
申请号：US11182848
申请日：2005-07-18
申请人： Jin Takahashi
发明人： Jin Takahashi
IPC分类号： G06F11/00
CPC分类号： G06F11/0772
摘要： An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system in a mirror mode. The error notification method generates an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels, reduces the error level of a corresponding error interrupt signal when the error within the first processor system is avoided in the mirror mode, and notifies the error to each processor within the first and second processor systems using the error interrupt signal.

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