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1. 发明授权

US07030728B2 Layout and method to improve mixed-mode resistor performance 有权
标题翻译：布局和方法来提高混合电阻的性能
公开(公告)号：US07030728B2
公开(公告)日：2006-04-18
申请号：US10831848
申请日：2004-04-26
申请人： Kong-Beng Thei , Chih-Hsien Lin , Shyh-Chyi Wong
发明人： Kong-Beng Thei , Chih-Hsien Lin , Shyh-Chyi Wong
IPC分类号： H01C1/012
CPC分类号： H01L28/20 , H01C7/006 , H01C17/0656 , H01C17/075 , H01L27/0802 , Y10T29/49082 , Y10T29/49087 , Y10T29/49098
摘要： A resistor layout and method of forming the resistor are described which achieves improved resistor characteristics, such as resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first resistor element, a second resistor element, a third resistor element, a fourth resistor element, and a fifth resistor element. A layer of protective dielectric is then formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide, such as titanium silicide or cobalt silicide, using a silicidation process. The higher conductivity silicide forms low resistance contacts between the second and fourth resistor elements and between the third and fifth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element, which is the main resistor element. This provides low voltage coefficient of resistance thermal process stability for the resistor.
摘要翻译：描述了形成电阻器的电阻器布局和方法，其实现了电阻器稳定性和电阻电压系数的改善的电阻器特性。电阻器由诸如掺杂硅或多晶硅的导电材料形成。电阻器具有矩形的第一电阻元件，第二电阻元件，第三电阻元件，第四电阻元件和第五电阻元件。然后在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。然后，使用硅化工艺将暴露的第四和第五电阻器元件中的导电材料改变为硅化物，例如硅化钛或硅化钴。较高电导率的硅化物在第二和第四电阻元件之间以及第三和第五电阻器元件之间形成低电阻触点。第二和第三电阻器元件比第一电阻器元件宽，并且向作为主电阻器元件的第一电阻器元件提供低电阻触点。这为电阻器提供了低电阻系数的电阻热处理稳定性。

2. 发明授权

US06732422B1 Method of forming resistors 有权
标题翻译：形成电阻的方法
公开(公告)号：US06732422B1
公开(公告)日：2004-05-11
申请号：US10037811
申请日：2002-01-04
申请人： Kong-Beng Thei , Chih-Hsien Lin , Shyh-Chyi Wong
发明人： Kong-Beng Thei , Chih-Hsien Lin , Shyh-Chyi Wong
IPC分类号： H01C1700
CPC分类号： H01L28/20 , H01C7/006 , H01C17/0656 , H01C17/075 , H01L27/0802 , Y10T29/49082 , Y10T29/49087 , Y10T29/49098
摘要： A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.
摘要翻译：描述形成电阻器的方法，其实现了电阻器稳定性和电阻的电压系数的改善。电阻器由诸如掺杂硅或多晶硅的导电材料形成。电阻器具有矩形的第一，第二，第三，第四和第五电阻元件。在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。然后将暴露的第四和第五电阻器元件中的导电材料改变为硅化物以在第二和第四电阻器元件之间以及第二和第四电阻器元件之间形成低电阻触点。第二和第三电阻器元件比第一电阻器元件宽，并且向第一电阻器元件提供低电阻触点。这为电阻器提供了低电阻系数和热处理稳定性。

3. 发明授权

US06426250B1 High density stacked MIM capacitor structure 有权
标题翻译：高密度堆叠MIM电容器结构
公开(公告)号：US06426250B1
公开(公告)日：2002-07-30
申请号：US09863225
申请日：2001-05-24
申请人： Tzyh-Cheang Lee , Shyh-Chyi Wong , Chih-Hsien Lin , Chi-Feng Huang
发明人： Tzyh-Cheang Lee , Shyh-Chyi Wong , Chih-Hsien Lin , Chi-Feng Huang
IPC分类号： H01L218242
CPC分类号： H01L28/90 , Y10S438/957
摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.
摘要翻译：在第一电介质层中形成第一金属插头。产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。

4. 发明申请

US20050132549A1 Method for making metal capacitors with low leakage currents for mixed-signal devices 审中-公开
标题翻译：混合信号器件制造漏电流低的金属电容器的方法
公开(公告)号：US20050132549A1
公开(公告)日：2005-06-23
申请号：US10853459
申请日：2004-05-25
申请人： Wong-Cheng Shih , Wen-Chi Ting , Tzyh-Cheang Lee , Chih-Hsien Lin , Shyh-Chyi Wong
发明人： Wong-Cheng Shih , Wen-Chi Ting , Tzyh-Cheang Lee , Chih-Hsien Lin , Shyh-Chyi Wong
IPC分类号： H01L21/02 , H01L21/316 , H01G9/00
CPC分类号： H01L28/40 , H01L21/31604 , H01L28/56 , Y10T29/43 , Y10T29/435
摘要： A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.
摘要翻译：实现了制造具有高介电常数绝缘体并夹在宽带隙绝缘体之间的金属绝缘体金属（MIM）电容器的方法，导致低漏电流和每单位面积的高电容。高k层增加下一代混合信号器件的单位面积电容，而宽带绝缘子减少泄漏电流。在第二实施例中，在宽带绝缘体之间形成不同的高k材料的多层以大大增加每单位面积的电容。优化了层材料和厚度，以减少非线性电容对电压的依赖性。

5. 发明授权

US06559493B2 High density stacked mim capacitor structure 有权
标题翻译：高密度堆叠式电容器结构
公开(公告)号：US06559493B2
公开(公告)日：2003-05-06
申请号：US10167864
申请日：2002-06-11
申请人： Tzyh-Cheang Lee , Shyh-Chyi Wong , Chih-Hsien Lin , Chi-Feng Huang
发明人： Tzyh-Cheang Lee , Shyh-Chyi Wong , Chih-Hsien Lin , Chi-Feng Huang
IPC分类号： H01L31119
CPC分类号： H01L28/90 , Y10S438/957
摘要： A first metal plug is formed in the first layer of dielectric. A freestanding second metal plug is created that aligns with and makes contact with the first metal plug, extending the first metal plug. The second metal plug is surrounded by an opening that has been created in layers of etch stop and dielectric. A layer of capacitor dielectric is deposited over the exposed surfaces of the first and second metal plugs and the inside surfaces of the opening that surrounds the second plug. A layer of metal is created over the capacitor dielectric inside the opening in the layers of etch stop and dielectric.
摘要翻译：在第一电介质层中形成第一金属插头。产生独立的第二金属插头，其与第一金属插头对准并与第一金属插头接触，延伸第一金属插头。第二个金属插塞由已经在蚀刻停止层和电介质层上形成的开口围绕。电容器电介质层沉积在第一和第二金属插头的暴露表面和围绕第二插头的开口的内表面中。在蚀刻停止层和电介质层的开口内部的电容器电介质上形成一层金属。

6. 发明授权

US06436787B1 Method of forming crown-type MIM capacitor integrated with the CU damascene process 有权
标题翻译：与CU镶嵌工艺集成的冠型MIM电容器的形成方法
公开(公告)号：US06436787B1
公开(公告)日：2002-08-20
申请号：US09912735
申请日：2001-07-26
申请人： Wong-Cheng Shih , Tzyh-Cheang Lee , Wenchi Ting , Chih-Hsien Lin , Shyh-Chyi Wong
发明人： Wong-Cheng Shih , Tzyh-Cheang Lee , Wenchi Ting , Chih-Hsien Lin , Shyh-Chyi Wong
IPC分类号： H01L2120
CPC分类号： H01L28/55 , H01L21/3212 , H01L28/75 , H01L28/91
摘要： A method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is described. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is is deposited overlying the first metal layer. A dielectric layer is dpeosited overlying the first barrier metal layer. A second barrier metal layer is deposited overlying the dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening. The layers are polished back to leave the first metal layer, the dielectric layer, the first and second barrier metal layers, and the second metal layer only within the damascene opening wherein the first metal layer forms a bottom electrode, the dielectric layer forms a capacitor dielectric, and the second metal layer forms a top electrode to complete fabrication of a crown-type capacitor in the fabrication of an integrated circuit device.
摘要翻译：描述了使用集成铜镶嵌工艺制造增加的电容金属 - 绝缘体 - 金属电容器的方法。提供覆盖半导体衬底的接触节点。沉积在接触节点上的金属间介电层。通过金属间介质层向接触节点形成镶嵌开口。第一金属层形成在镶嵌开口的底部和侧壁上并覆盖金属间介电层。第一阻挡金属层被沉积在第一金属层上。介电层被覆在第一阻挡金属层上方。沉积在电介质层上的第二阻挡金属层。形成第二金属层，覆盖第二阻挡金属层并完全填充镶嵌开口。这些层被抛光回去，以留下第一金属层，电介质层，第一和第二阻挡金属层和第二金属层，仅在镶嵌开口内，其中第一金属层形成底部电极，电介质层形成电容器电介质，并且第二金属层形成顶部电极，以在集成电路器件的制造中完成冠型电容器的制造。

7. 发明授权

US08368445B2 Delay-locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US08368445B2
公开(公告)日：2013-02-05
申请号：US13174798
申请日：2011-07-01
申请人： Chih-Hsien Lin , Chih-Wei Mu , Ming-Shih Yu
发明人： Chih-Hsien Lin , Chih-Wei Mu , Ming-Shih Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0816 , H03L7/087 , H03L7/1075
摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.
摘要翻译：提供接收参考时钟信号并输出输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

8. 发明授权

US08151995B2 Methods and apparatus to prevent mold compound feeder jams in systems to package integrated circuits 有权
标题翻译：防止模具复合供料器卡纸在系统中封装集成电路的方法和装置
公开(公告)号：US08151995B2
公开(公告)日：2012-04-10
申请号：US12025332
申请日：2008-02-04
申请人： Chih-Chung Chen , Chih-Hsien Lin , Tsung-Chi Chiang
发明人： Chih-Chung Chen , Chih-Hsien Lin , Tsung-Chi Chiang
IPC分类号： B07C5/00
CPC分类号： B29C45/76 , B29C45/14639
摘要： Methods and apparatus to preventing mold feeder jams in a system to package integrated circuits. An example method includes detecting if a mold compound tablet has a first alignment on a path and removing the mold compound tablet from the path if the mold compound tablet has a second alignment different from the first alignment.
摘要翻译：用于防止系统中的模具给料器卡纸封装集成电路的方法和装置。示例性方法包括检测模具复合片剂是否具有路径上的第一对准并且如果模制复合片剂具有不同于第一对准的第二取向，则从路径移除模具复合片剂。

9. 发明授权

US07220677B2 WAT process to avoid wiring defects 有权
标题翻译： WAT过程避免接线缺陷
公开(公告)号：US07220677B2
公开(公告)日：2007-05-22
申请号：US11106120
申请日：2005-04-13
申请人： Lin-Ping Li , Yung-Cheng Lu , Wen-Chih Chiou , Chih-Hsien Lin
发明人： Lin-Ping Li , Yung-Cheng Lu , Wen-Chih Chiou , Chih-Hsien Lin
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L22/10 , G01R31/2831 , H01L21/76838 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.
摘要翻译：一种用于形成多级半导体器件以在WAT测试之后消除导电互连突起的方法，所述方法包括形成第一金属化层; 进行晶圆验收测试（WAT）工艺; 然后在金属化层上进行化学机械抛光（CMP）。

10. 发明授权

US06873778B2 Fiber container and associated optical communication device 失效
标题翻译：光纤容器及相关光通讯装置
公开(公告)号：US06873778B2
公开(公告)日：2005-03-29
申请号：US10291836
申请日：2002-11-12
申请人： Tsung-Yueh Tsai , Chin-Hsiang Wang , Yu-Ting Lee , Chih-Hsien Lin
发明人： Tsung-Yueh Tsai , Chin-Hsiang Wang , Yu-Ting Lee , Chih-Hsien Lin
IPC分类号： B65H18/08 , G02B6/00 , H01S3/067
CPC分类号： H01S3/06704
摘要： A fiber container receiving optical fibers has a body, a space defined in the body, a reel disposed inside the body, wherein a groove is defined around the periphery of the reel. The optical fibers are twisted around the reel and received in the groove. Furthermore, the fiber container is able to apply to the active/passive optical communication device, such as an erbium doped fiber amplifier (EDFA) or a dense wavelength division multiplexer (DWDM).
摘要翻译：容纳光纤的纤维容器具有主体，在主体中限定的空间，设置在主体内部的卷轴，其中围绕卷轴的周边限定有凹槽。光纤绕卷轴扭转并被接收在槽中。此外，光纤容器能够应用于有源/无源光通信设备，例如掺铒光纤放大器（EDFA）或密集波分复用器（DWDM）。

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