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1. 发明申请

US20130002320A1 DELAY-LOCKED LOOP 有权
标题翻译：延迟锁定
公开(公告)号：US20130002320A1
公开(公告)日：2013-01-03
申请号：US13174798
申请日：2011-07-01
申请人： Chih-Hsien Lin , Chih-Wei Mu , Ming-Shih Yu
发明人： Chih-Hsien Lin , Chih-Wei Mu , Ming-Shih Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0816 , H03L7/087 , H03L7/1075
摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.
摘要翻译：提供接收参考时钟信号并输出输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

2. 发明授权

US08368445B2 Delay-locked loop 有权
标题翻译：延迟锁定环路
公开(公告)号：US08368445B2
公开(公告)日：2013-02-05
申请号：US13174798
申请日：2011-07-01
申请人： Chih-Hsien Lin , Chih-Wei Mu , Ming-Shih Yu
发明人： Chih-Hsien Lin , Chih-Wei Mu , Ming-Shih Yu
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0816 , H03L7/087 , H03L7/1075
摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.
摘要翻译：提供接收参考时钟信号并输出输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

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