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1. 外观设计

USD640230S1 Voice recording/reproducing device 有权
公开(公告)号：USD640230S1
公开(公告)日：2011-06-21
申请号：US29382111
申请日：2010-12-29
申请人： Koji Sakai , Yoshihiro Hayashi
设计人： Koji Sakai , Yoshihiro Hayashi

2. 外观设计

USD640229S1 Voice recording/reproducing device 有权
公开(公告)号：USD640229S1
公开(公告)日：2011-06-21
申请号：US29382110
申请日：2010-12-29
申请人： Koji Sakai , Yoshihiro Hayashi
设计人： Koji Sakai , Yoshihiro Hayashi

3. 外观设计

USD640228S1 Voice recording/reproducing device 有权
公开(公告)号：USD640228S1
公开(公告)日：2011-06-21
申请号：US29382106
申请日：2010-12-29
申请人： Koji Sakai , Yoshihiro Hayashi
设计人： Koji Sakai , Yoshihiro Hayashi

4. 发明授权

US08937023B2 Method of manufacturing porous insulating film 有权
标题翻译：多孔绝缘膜的制造方法
公开(公告)号：US08937023B2
公开(公告)日：2015-01-20
申请号：US13363638
申请日：2012-02-01
申请人： Fuminori Ito , Yoshihiro Hayashi
发明人： Fuminori Ito , Yoshihiro Hayashi
IPC分类号： H01L23/48 , H01L21/316 , C23C16/40 , C23C18/12 , C23C18/14 , H01L21/02
CPC分类号： H01L21/31695 , C23C16/401 , C23C18/1212 , C23C18/122 , C23C18/14 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02348 , H01L21/02362
摘要： A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
摘要翻译：一种方法包括通过引入具有环状硅氧烷作为骨架并具有至少一个与侧链结合的挥发性烃基的环状硅氧烷化合物，将含硅化合物引入等离子体中，在基板上形成绝缘膜，通过向绝缘膜添加能量将绝缘膜与多孔绝缘膜接合。与环状硅氧烷化合物，挥发性烃基，环状硅氧烷化合物和挥发性烃基的键相比，含硅化合物的分解能力较少。

5. 发明授权

US08648441B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08648441B2
公开(公告)日：2014-02-11
申请号：US13106590
申请日：2011-05-12
申请人： Kenichiro Hijioka , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
发明人： Kenichiro Hijioka , Ippei Kume , Naoya Inoue , Hiroki Shirai , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L21/02
CPC分类号： H01L27/10894 , H01L21/76811 , H01L23/5223 , H01L27/10852 , H01L28/75 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.
摘要翻译：半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

6. 发明授权

US08629529B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US08629529B2
公开(公告)日：2014-01-14
申请号：US12519706
申请日：2007-12-25
申请人： Naoya Inoue , Ippei Kume , Jun Kawahara , Yoshihiro Hayashi
发明人： Naoya Inoue , Ippei Kume , Jun Kawahara , Yoshihiro Hayashi
IPC分类号： H01L27/06
CPC分类号： H01L23/5228 , H01L23/5223 , H01L23/53238 , H01L27/0688 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.
摘要翻译：通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。因此，即使下电极的膜厚变薄，寄生电阻也不会增加。电阻元件形成为具有与电容器元件的下电极相同的膜厚度。由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

7. 发明授权

US08624328B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08624328B2
公开(公告)日：2014-01-07
申请号：US12591089
申请日：2009-11-06
申请人： Jun Kawahara , Yoshihiro Hayashi , Ippei Kume
发明人： Jun Kawahara , Yoshihiro Hayashi , Ippei Kume
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Provided is a semiconductor device including: a semiconductor substrate; a multi-layered wiring structure which is formed over the semiconductor substrate and in which a plurality of wiring layers, each of which is formed by a wiring and an insulating layer, are laminated; and a capacitive element having a lower electrode, a capacitor insulating layer, and an upper electrode which is embedded in the multi-layered wiring structure, wherein at least two or more of the wiring layers are provided between a lower capacitor wiring connected to the lower electrode and an upper capacitor wiring connected to the upper electrode.
摘要翻译：提供一种半导体器件，包括：半导体衬底; 形成在半导体衬底上并且其中由布线和绝缘层形成的多个布线层被层叠的多层布线结构; 以及具有嵌入在所述多层布线结构中的下电极，电容绝缘层和上电极的电容元件，其特征在于，所述布线层中的至少两个以上设置在与所述下层电极电极和连接到上电极的上电容器布线。

8. 发明授权

US08618537B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08618537B2
公开(公告)日：2013-12-31
申请号：US13067386
申请日：2011-05-27
申请人： Kishou Kaneko , Naoya Inoue , Yoshihiro Hayashi
发明人： Kishou Kaneko , Naoya Inoue , Yoshihiro Hayashi
IPC分类号： H01L29/10
CPC分类号： H01L29/7869 , H01L27/0688 , H01L27/1225 , H01L27/124 , H01L27/1248 , H01L29/45 , H01L29/458
摘要： A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.
摘要翻译：半导体器件包括在半导体衬底上的第一区域中，第一绝缘层，第一布线，第二绝缘层，第三绝缘层以及嵌入第二绝缘层中的通孔和第二布线，以及第三绝缘层并且在第二区域中包括第一绝缘层，栅电极，第二绝缘层，位于第三绝缘层和第一导电体中的半导体层，以及嵌入在第二绝缘层中的第二导电体第三绝缘层，以通过势垒金属在平面图中将栅电极夹在与半导体层重叠的位置，并通过阻挡金属耦合到半导体层。

9. 发明授权

US08435828B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08435828B2
公开(公告)日：2013-05-07
申请号：US13006034
申请日：2011-01-13
申请人： Hironori Yamamoto , Yoshihiro Hayashi , Jun Kawahara , Tatsuya Usami , Koichi Ohto
发明人： Hironori Yamamoto , Yoshihiro Hayashi , Jun Kawahara , Tatsuya Usami , Koichi Ohto
IPC分类号： H01L51/40
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/022 , H01L21/02203 , H01L21/02274 , H01L21/76826 , H01L21/76829 , H01L21/76883
摘要： A method of manufacturing a semiconductor device includes forming a first insulating film over an underlying film by plasma polymerization of cyclic siloxane, and forming a second insulating film on the first insulating film by plasma polymerization of the cyclic siloxane continuously, after forming the first insulating film. The deposition rate of the first insulating film is slower than the deposition rate of the second insulating film.
摘要翻译：一种制造半导体器件的方法包括：通过环状硅氧烷的等离子体聚合在下面的膜上形成第一绝缘膜，并且在形成第一绝缘膜之后，通过环状硅氧烷的等离子体聚合在第一绝缘膜上形成第二绝缘膜。第一绝缘膜的沉积速度比第二绝缘膜的沉积速度慢。

10. 发明申请

US20120249227A1 VOLTAGE LEVEL GENERATOR CIRCUIT 审中-公开
标题翻译：电压电平发生器电路
公开(公告)号：US20120249227A1
公开(公告)日：2012-10-04
申请号：US13350795
申请日：2012-01-15
申请人： Ryo NAKAYAMA , Masaki Yoshinaga , Yoshitaka Abe , Kenji Hirayama , Yoshihiro Hayashi
发明人： Ryo NAKAYAMA , Masaki Yoshinaga , Yoshitaka Abe , Kenji Hirayama , Yoshihiro Hayashi
IPC分类号： G05F3/02
CPC分类号： G05F3/20
摘要： A voltage level generator circuit comprised of a fixed voltage generator unit for generating a first electrical current in a fixed quantity from a first supply voltage; a first current mirror circuit unit including a first thin-film NMOSFET and a second thin-film NMOSFET and that outputs a second electrical current proportional to the first electrical current; a protective circuit including: a third thin-film NMOSFET and a first thick-film PMOSFET utilized as a grounded gate for protecting the second thin-film NMOSFET, a first diode for preventing inverse current flow to the first supply, and a second diode for preventing the gate-source voltage of the third thin-film NMOSFET from reaching a negative electrical potential; and a second current mirror circuit for outputting a third electrical current proportional to the second electrical current; and a first Zener diode unit for generating a first fixed voltage from a third electrical current.
摘要翻译：一种电压电平发生器电路，包括：固定电压发生器单元，用于从第一电源电压产生固定量的第一电流; 第一电流镜电路单元，包括第一薄膜NMOSFET和第二薄膜NMOSFET，并且输出与第一电流成比例的第二电流; 保护电路，包括：第三薄膜NMOSFET和用作保护第二薄膜NMOSFET的接地栅极的第一厚膜PMOSFET，用于防止反向电流流向第一电源的第一二极管和用于防止第三薄膜NMOSFET的栅极 - 源极电压达到负电位; 以及第二电流镜电路，用于输出与第二电流成比例的第三电流; 以及用于从第三电流产生第一固定电压的第一齐纳二极管单元。

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