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1. 发明授权

US08458409B2 Access controller 有权
标题翻译：门禁控制器
公开(公告)号：US08458409B2
公开(公告)日：2013-06-04
申请号：US12598478
申请日：2009-03-02
申请人： Koji Asai , Takashi Morimoto , Ryuta Nakanishi
发明人： Koji Asai , Takashi Morimoto , Ryuta Nakanishi
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： An access control apparatus receives access requests from one or more regular masters and an irregular master and sequentially selects an access allowable target. Additionally, the access control apparatus calculates an amount of unused resources based on an amount of resources used by a regular master and a maximum amount of resources to be used by the regular master, and manages the unused resources. The access control apparatus selects an access request of an irregular master as an access allowable target when the irregular master makes the access request during a unit period and access based on an access request of at least one of the regular masters that has not been executed. The managed amount of unused resources is equal to or larger than an amount of resources which is to be used based on the access request of the irregular master.
摘要翻译：访问控制装置接收来自一个或多个常规主机和不规则主机的访问请求，并且顺序地选择访问许可目标。此外，访问控制装置基于正常主机使用的资源量和常规主机将要使用的最大资源量来计算未使用资源的量，并且管理未使用的资源。当不规则主机在单位期间内进行访问请求时，访问控制装置根据至少一个尚未执行的常规主机的访问请求来访问不规则主机的访问请求作为访问允许目标。未使用资源的管理量等于或大于基于不规则主机的访问请求要使用的资源量。

2. 发明申请

US20100122040A1 ACCESS CONTROLLER 有权
标题翻译：访问控制器
公开(公告)号：US20100122040A1
公开(公告)日：2010-05-13
申请号：US12598478
申请日：2009-03-02
申请人： Koji Asai , Takashi Morimoto , Ryuta Nakanishi
发明人： Koji Asai , Takashi Morimoto , Ryuta Nakanishi
IPC分类号： G06F12/00
CPC分类号： G06F13/1663
摘要： The present invention aims to provide an access control apparatus that can improve responsiveness to an access request of a processor compared with a conventional technology.The access control apparatus, which receives access requests from one or more regular masters and a irregular master and sequentially selects an access allowable target, calculates an amount of unused resources based on an amount of resources used by a regular master which makes an access request during a unit period and a maximum amount of resources to be used given to the regular master and manages it. The access control apparatus selects an access request of the irregular master as an access allowable target when the irregular master makes the access request during the unit period and an access based on the access request of at least one of the regular masters has not been executed, and a total of the managed amount of unused resources is equal to or larger than an amount of resources which is to be used based on the access request of the irregular master.
摘要翻译：本发明的目的在于提供一种访问控制装置，其可以提高与常规技术相比对处理器的访问请求的响应性。接收控制装置，其接收来自一个或多个常规主机和不规则主机的接入请求，并且依次选择访问可允许目标，基于由正常主机使用的资源量来计算未使用资源量一个单位时期和给予普通大师的最大资源数量并进行管理。当不规则主机在单位期间内进行访问请求时，访问控制装置选择不规则主机的访问请求作为访问允许目标，并且基于至少一个常规主机的访问请求的访问尚未被执行，并且未使用资源的管理量的总和等于或大于基于不规则主控的访问请求将要使用的资源量。

3. 发明申请

US20100042751A1 DATA TRANSFER CONTROL DEVICE, DATA TRANSFER DEVICE, DATA TRANSFER CONTROL METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT USING RECONFIGURED CIRCUIT 审中-公开
标题翻译：数据传输控制设备，数据传输设备，数据传输控制方法和使用重新配置的电路的半导体集成电路
公开(公告)号：US20100042751A1
公开(公告)日：2010-02-18
申请号：US12522490
申请日：2008-10-24
申请人： Kouichi Ishino , Takashi Morimoto , Koji Asai
发明人： Kouichi Ishino , Takashi Morimoto , Koji Asai
IPC分类号： G06F3/00
CPC分类号： G11C7/10 , G06F13/1694
摘要： A semiconductor integrated circuit ensures to reserve a required memory bandwidth at low cost. A memory bandwidth monitoring unit 1210 calculates a required memory bandwidth, monitors the usage condition of the memory, and outputs the following information to a reconfiguration control unit 1120. The information is necessary to reconfigure a reconfiguration unit 1110 into a logic unit and a temporary buffer both of which are scalable depending on the usage condition. According to information, the reconfiguration control unit 1120 controls the reconfiguration unit 1110. The buffer is for storing data accessed to or from the memory by each bus master. The logic unit acts as a bus master that only uses a portion of the memory bandwidth that remains unused during the time no access request to the data storage unit 1002 issued by a bus master unit having a higher priority level is being executed.
摘要翻译：半导体集成电路确保以低成本保留所需的存储器带宽。存储器带宽监视单元1210计算所需的存储器带宽，监视存储器的使用状况，并将以下信息输出到重新配置控制单元1120.该信息对于将重新配置单元1110重新配置为逻辑单元和临时缓冲器这两者都可以根据使用条件进行扩展。根据信息，重新配置控制单元1120控制重新配置单元1110.缓冲器用于存储由每个总线主机访问或从存储器访问的数据。逻辑单元充当总线主机，其仅在没有执行具有较高优先级的总线主机单元发出的对数据存储单元1002的访问请求的时间内仅使用保持未使用的存储器带宽的一部分。

4. 发明申请

US20100023736A1 RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE 审中-公开
标题翻译：可重构电路，复位方法和配置信息生成装置
公开(公告)号：US20100023736A1
公开(公告)日：2010-01-28
申请号：US12520909
申请日：2008-10-30
申请人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
发明人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
IPC分类号： G06F9/00 , G06F9/30 , G06F9/45
CPC分类号： H03K19/17772 , G06F1/24 , H03K19/17756 , H03K19/1776
摘要： The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.
摘要翻译：本发明提供一种可重构电路，其包括多个重新配置单元，并且改变每个重新配置单元中包括的计算处理单元的配置。这里，每个重新配置单元还包括：计算存储单元，用于存储由计算处理单元执行的计算结果; 标记保持单元，用于保持指示是否需要计算存储单元的初始化的初始化标志; 以及初始化控制单元，其可操作以在所述计算处理单元的配置改变期间，基于由所述标志保持单元保持的初始化标志来控制所述计算存储单元的初始化。

5. 发明授权

US08601192B2 Arbitration device, arbitration system, arbitration method, semiconductor integrated circuit, and image processing device 有权
标题翻译：仲裁装置，仲裁系统，仲裁方法，半导体集成电路和图像处理装置
公开(公告)号：US08601192B2
公开(公告)日：2013-12-03
申请号：US13057019
申请日：2010-06-04
申请人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
发明人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G06F13/1605 , G06F13/362 , Y02D10/14
摘要： Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.
摘要翻译：提供了一种分级仲裁装置，其中，层级的每个级别的仲裁装置选择具有最高优先级的资源使用请求和具有第二高优先级的资源使用请求，将这两个资源使用请求输出到作为一级的仲裁装置更高。在将优先级最高的存储器使用请求作为最高优先级资源使用请求输出到资源控制单元之后，当层级最高级别的仲裁装置接收到来自存储器控制单元的指示接收资源使用请求的信号时，仲裁装置然后选择具有第二高优先级的资源使用请求，并将该资源请求作为下一个优先权资源使用请求输出。

6. 发明申请

US20110138092A1 ARBITRATION DEVICE, ARBITRATION SYSTEM, ARBITRATION METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND IMAGE PROCESSING DEVICE 有权
标题翻译：仲裁设备，仲裁系统，仲裁方法，半导体集成电路和图像处理设备
公开(公告)号：US20110138092A1
公开(公告)日：2011-06-09
申请号：US13057019
申请日：2010-06-04
申请人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
发明人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
IPC分类号： G06F13/362 , G06F12/00
CPC分类号： G06F13/1605 , G06F13/362 , Y02D10/14
摘要： Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.
摘要翻译：提供了一种分级仲裁装置，其中，层级的每个级别的仲裁装置选择具有最高优先级的资源使用请求和具有第二高优先级的资源使用请求，将这两个资源使用请求输出到作为一级的仲裁装置更高。在将优先级最高的存储器使用请求作为最高优先级资源使用请求输出到资源控制单元之后，当层级最高级别的仲裁装置接收到来自存储器控制单元的指示接收资源使用请求的信号时，仲裁装置然后选择具有第二高优先级的资源使用请求，并将该资源请求作为下一个优先权资源使用请求输出。

7. 发明授权

US09109598B2 Compressor with oil separating mechanism 有权
标题翻译：带油分离机构的压缩机
公开(公告)号：US09109598B2
公开(公告)日：2015-08-18
申请号：US13812347
申请日：2012-03-15
申请人： Atsushi Sakuda , Yoshiyuki Futagami , Hiroyuki Kawano , Yusuke Imai , Takashi Morimoto , Osamu Aiba , Takeshi Hashimoto
发明人： Atsushi Sakuda , Yoshiyuki Futagami , Hiroyuki Kawano , Yusuke Imai , Takashi Morimoto , Osamu Aiba , Takeshi Hashimoto
IPC分类号： F04C18/00 , F04C23/00 , F04C29/02 , F04C18/02 , F04B39/16
CPC分类号： F04C18/00 , F04B39/16 , F04C18/0215 , F04C18/0253 , F04C18/0261 , F04C23/008 , F04C29/026
摘要： According to a compressor of the present invention, the compressor further comprises an oil separating mechanism 40 which separates oil from the refrigerant gas discharged from the compressing mechanism 10, the oil separating mechanism 40 includes a cylindrical space 41 in which the refrigerant gas orbits, an inflow portion 42 for flowing the refrigerant gas discharged from the compressing mechanism 10 into the cylindrical space 41, a sending-out port 43 for sending out, from the cylindrical space 41 to the one container space 32, the refrigerant gas from which the oil is separated, and an exhaust port 44 for discharging the separated oil from the cylindrical space 41 into the other container space 32. According to this configuration, efficiency of the electric motor 20 is enhanced, volumetric efficiency is enhanced, and low oil circulation is realized.
摘要翻译：根据本发明的压缩机，压缩机还包括分油机构40，其将油与从压缩机构10排出的制冷剂气体分离，油分离机构40包括制冷剂气体在其中轨道运动的圆柱形空间41，用于将从压缩机构10排出的制冷剂气体流入圆筒形空间41的流出部分42，从圆筒形空间41向一个容器空间32排出油的制冷剂气体的送出口43 以及用于将分离的油从圆筒空间41排出到另一个容器空间32中的排气口44.根据该结构，电动机20的效率提高，容积效率提高，油循环低。

8. 发明授权

US08824236B2 Memory access control device and manufacturing method 有权
标题翻译：存储器访问控制装置及其制造方法
公开(公告)号：US08824236B2
公开(公告)日：2014-09-02
申请号：US13811482
申请日：2012-02-21
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G11C8/00 , G06F13/00 , G11C8/04 , G11C29/00
CPC分类号： G11C8/04 , G06F13/00 , G11C29/00 , G11C29/022 , G11C29/4401 , G11C29/822 , H01L2224/16225
摘要： A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
摘要翻译：一种存储器访问控制装置，包括：比特位置信息存储单元，存储指示预定长度的比特序列中的一个或多个比特位置的比特位置信息; 读取单元，被配置为尝试从由逻辑地址接收单元接收的逻辑地址指定的范围内读取比特序列，从而以预定长度为单位从外部存储器接收第一比特序列，第一比特序列被组合的位数大于存储在由逻辑地址指定的范围内的位数; 比特序列提取单元，被配置为以由所述比特位置信息指定的所述一个或多个比特位置以所述预定长度为单位从所述第一比特序列提取一个或多个比特序列。

9. 发明授权

US08566762B2 Three-dimensional integrated circuit design device, three-dimensional integrated circuit design, method, and program 有权
标题翻译：三维集成电路设计器件，三维集成电路设计，方法和程序
公开(公告)号：US08566762B2
公开(公告)日：2013-10-22
申请号：US13637818
申请日：2012-02-17
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G06F17/50
CPC分类号： H01L27/0211 , G06F17/505 , H01L27/0688
摘要： A worst-case temperature calculation unit calculates, based on heat value information of each layer of a three-dimensional integrated circuit to be designed and stack structure information of the three-dimensional integrated circuit, a worst-case temperature of a layer during operation that is targeted for logic synthesis. A logic synthesis library selection unit selects a library appropriate for the calculated worst-case temperature. A logic synthesis unit performs logic synthesis on the targeted layer with use of the selected library.
摘要翻译：最坏情况温度计算单元基于要设计的三维集成电路的每层的热值信息和三维集成电路的堆叠结构信息来计算操作期间的层的最坏情况温度，是逻辑综合的目标。逻辑合成库选择单元选择适合于计算的最坏情况温度的库。逻辑合成单元使用所选择的库来对目标层执行逻辑合成。

10. 发明申请

US20130121093A1 MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD 有权
标题翻译：存储器访问控制装置和制造方法
公开(公告)号：US20130121093A1
公开(公告)日：2013-05-16
申请号：US13811482
申请日：2012-02-21
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G11C8/04
CPC分类号： G11C8/04 , G06F13/00 , G11C29/00 , G11C29/022 , G11C29/4401 , G11C29/822 , H01L2224/16225
摘要： A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
摘要翻译：一种存储器访问控制装置，包括：比特位置信息存储单元，存储指示预定长度的比特序列中的一个或多个比特位置的比特位置信息; 读取单元，被配置为尝试从由逻辑地址接收单元接收的逻辑地址指定的范围内读取比特序列，从而以预定长度为单位从外部存储器接收第一比特序列，第一比特序列被组合的位数大于存储在由逻辑地址指定的范围内的位数; 比特序列提取单元，被配置为以由所述比特位置信息指定的所述一个或多个比特位置以所述预定长度为单位从所述第一比特序列提取一个或多个比特序列。

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