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1. 发明授权

US08601192B2 Arbitration device, arbitration system, arbitration method, semiconductor integrated circuit, and image processing device 有权
标题翻译：仲裁装置，仲裁系统，仲裁方法，半导体集成电路和图像处理装置
公开(公告)号：US08601192B2
公开(公告)日：2013-12-03
申请号：US13057019
申请日：2010-06-04
申请人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
发明人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G06F13/1605 , G06F13/362 , Y02D10/14
摘要： Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.
摘要翻译：提供了一种分级仲裁装置，其中，层级的每个级别的仲裁装置选择具有最高优先级的资源使用请求和具有第二高优先级的资源使用请求，将这两个资源使用请求输出到作为一级的仲裁装置更高。在将优先级最高的存储器使用请求作为最高优先级资源使用请求输出到资源控制单元之后，当层级最高级别的仲裁装置接收到来自存储器控制单元的指示接收资源使用请求的信号时，仲裁装置然后选择具有第二高优先级的资源使用请求，并将该资源请求作为下一个优先权资源使用请求输出。

2. 发明申请

US20110138092A1 ARBITRATION DEVICE, ARBITRATION SYSTEM, ARBITRATION METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND IMAGE PROCESSING DEVICE 有权
标题翻译：仲裁设备，仲裁系统，仲裁方法，半导体集成电路和图像处理设备
公开(公告)号：US20110138092A1
公开(公告)日：2011-06-09
申请号：US13057019
申请日：2010-06-04
申请人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
发明人： Takashi Morimoto , Yoshiharu Watanabe , Takashi Yamada , Takashi Hashimoto , Koji Asai
IPC分类号： G06F13/362 , G06F12/00
CPC分类号： G06F13/1605 , G06F13/362 , Y02D10/14
摘要： Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request.
摘要翻译：提供了一种分级仲裁装置，其中，层级的每个级别的仲裁装置选择具有最高优先级的资源使用请求和具有第二高优先级的资源使用请求，将这两个资源使用请求输出到作为一级的仲裁装置更高。在将优先级最高的存储器使用请求作为最高优先级资源使用请求输出到资源控制单元之后，当层级最高级别的仲裁装置接收到来自存储器控制单元的指示接收资源使用请求的信号时，仲裁装置然后选择具有第二高优先级的资源使用请求，并将该资源请求作为下一个优先权资源使用请求输出。

3. 发明申请

US20110035559A1 MEMORY CONTROLLER, MEMORY SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MEMORY CONTROL METHOD 有权
标题翻译：存储器控制器，存储器系统，半导体集成电路和存储器控制方法
公开(公告)号：US20110035559A1
公开(公告)日：2011-02-10
申请号：US12988396
申请日：2009-04-21
申请人： Koji Asai , Tetsuji Mochida , Daisuke Imoto , Takashi Yamada , Wataru Ohkoshi
发明人： Koji Asai , Tetsuji Mochida , Daisuke Imoto , Takashi Yamada , Wataru Ohkoshi
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F13/1642 , G06F8/4442 , G06F12/0862 , G06F2212/6022
摘要： A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.
摘要翻译：根据本发明的存储器控制器（101）包括：命令产生单元（102），其基于包括指示图像数据中的矩形区域的逻辑地址的访问请求，生成包括物理地址的访问命令; 以及向存储器（0）发出由命令生成单元（102）生成的访问命令的命令发布单元（105）。命令生成单元（102）包括：组决定单元（104），其基于与访问请求对应的物理地址，确定包含要访问的数据的存储体所属的组。命令生成单元（102）生成一对第一和第二访问命令，当要访问的数据在属于不同组的两个存储体中是连续的时，共享一个属于不同组的两个存储体之间的预取缓冲器。

4. 发明授权

US08918589B2 Memory controller, memory system, semiconductor integrated circuit, and memory control method 有权
标题翻译：存储控制器，存储器系统，半导体集成电路和存储器控制方法
公开(公告)号：US08918589B2
公开(公告)日：2014-12-23
申请号：US12988396
申请日：2009-04-21
申请人： Koji Asai , Tetsuji Mochida , Daisuke Imoto , Takashi Yamada , Wataru Ohkoshi
发明人： Koji Asai , Tetsuji Mochida , Daisuke Imoto , Takashi Yamada , Wataru Ohkoshi
IPC分类号： G06F12/02 , G06F13/16 , G06F12/08 , G06F9/45
CPC分类号： G06F13/1642 , G06F8/4442 , G06F12/0862 , G06F2212/6022
摘要： A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.
摘要翻译：根据本发明的存储器控制器（101）包括：命令产生单元（102），其基于包括指示图像数据中的矩形区域的逻辑地址的访问请求，生成包括物理地址的访问命令; 以及向存储器（0）发出由命令生成单元（102）生成的访问命令的命令发布单元（105）。命令生成单元（102）包括：组决定单元（104），其基于与访问请求对应的物理地址，确定包含要访问的数据的存储体所属的组。命令生成单元（102）生成一对第一和第二访问命令，当要访问的数据在属于不同组的两个存储体中是连续的时，共享一个属于不同组的两个存储体之间的预取缓冲器。

5. 发明授权

US08738888B2 Memory control device, memory device, and memory control method 有权
标题翻译：存储器控制装置，存储器件和存储器控制方法
公开(公告)号：US08738888B2
公开(公告)日：2014-05-27
申请号：US13615983
申请日：2012-09-14
申请人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
发明人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
IPC分类号： G06F12/12
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

6. 发明申请

US20100030980A1 MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD 有权
标题翻译：存储器控制装置，存储器装置和存储器控制方法
公开(公告)号：US20100030980A1
公开(公告)日：2010-02-04
申请号：US12443598
申请日：2007-12-25
申请人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
发明人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

7. 发明授权

US08307190B2 Memory control device, memory device, and memory control method 有权
标题翻译：存储器控制装置，存储器件和存储器控制方法
公开(公告)号：US08307190B2
公开(公告)日：2012-11-06
申请号：US12443598
申请日：2007-12-25
申请人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
发明人： Takashi Yamada , Daisuke Imoto , Koji Asai , Nobuyuki Ichiguchi , Tetsuji Mochida
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06T1/60
摘要： The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.
摘要翻译：根据本发明的存储器控制装置包括：命令生成单元，其将由主机发出的存储器访问请求分成对于存储器件中的一个的访问命令;命令发布单元，其将每个访问命令发布到存储器装置，在主机和存储器之间切换数据的数据控制单元和指令生成单元之间的切换，用于输出与存储器单元相同的物理地址的控制，并且根据何时根据时间向存储器装置输出不同的物理地址存储器件的物理地址相同，并且当存储器件的物理地址不同时，每个存储器件对应于分割的存取命令之一。

8. 发明授权

US08965146B2 Advanced-format optical modulator with low power consumption and low-loss characteristics 有权
标题翻译：高级格式的光调制器具有低功耗和低损耗特性
公开(公告)号：US08965146B2
公开(公告)日：2015-02-24
申请号：US13381298
申请日：2010-07-09
申请人： Takashi Goh , Yoshiyuki Doi , Shinji Mino , Ken Tsuzuki , Hiroshi Yamazaki , Takashi Yamada
发明人： Takashi Goh , Yoshiyuki Doi , Shinji Mino , Ken Tsuzuki , Hiroshi Yamazaki , Takashi Yamada
IPC分类号： G02F1/035 , G02F1/03 , G02F1/225 , G02B6/12
CPC分类号： G02F1/0327 , G02B2006/12142 , G02B2006/12159 , G02F1/225 , G02F2201/126 , G02F2203/20 , G02F2203/21
摘要： In a nest MZI modulator in which each arm includes a child MZI, the power consumption is reduced. The hybrid integrated-type nest MZI modulator of the embodiment 1a is configured so that, instead of placing a relative phase adjusting section in a parent MZI, a bias electrode Bias 90° in which an electric field is applied in the same direction to the polarization direction in both of the upper and lower arms is placed in each child MZI (see FIG. 4B). The bias electrode Bias 90° provided in each child MZI constitute the entirety of a relative phase adjusting section. The optical signals are subjected to a phase change after the output from the child MZI (see FIG. 1A), because such relative phase adjusting section can subject the optical signals of the upper and lower arms of the child MZI to a shift change in the same direction, respectively.
摘要翻译：在其中每个臂包括儿童MZI的巢MZI调制器中，功耗降低。实施例1a的混合集成型嵌套MZI调制器被配置为使得不是将相对相位调整部分放置在母MZI中，而是将偏置电极偏置90°，其中向与极化相同的方向施加电场将上臂和下臂两者的方向放置在每个子MZI中（参见图4B）。每个子MZI中设置的偏置电极偏置90°构成相对相位调整部的整体。在从子MZI（参见图1A）的输出之后，光信号经受相变，因为这种相对相位调整部分可以使子MZI的上臂和下臂的光信号在相同方向。

9. 发明申请

US20140015496A1 CHARGING DEVICE 审中-公开
标题翻译：充电设备
公开(公告)号：US20140015496A1
公开(公告)日：2014-01-16
申请号：US13933458
申请日：2013-07-02
申请人： Tadao Nishiguchi , Takashi Yamada , Hideyuki Yasugi , Masayuki Hanatani , Yusaku Ido
发明人： Tadao Nishiguchi , Takashi Yamada , Hideyuki Yasugi , Masayuki Hanatani , Yusaku Ido
IPC分类号： H02J7/00
CPC分类号： H02J7/007 , H02J7/022 , H02M1/42 , H02M3/33507 , H02M2001/007 , H02M2001/4291 , Y02B40/90 , Y02B70/12 , Y02B70/126
摘要： A charging device has an AC power supply input part that rectifies an AC voltage, a power factor correction part that converts a rectified voltage outputted from the AC power supply input part into a DC intermediate voltage, a power conversion part that converts the intermediate voltage outputted from the power factor correction part into a charge voltage, and supplies the charge voltage to a secondary battery, an input voltage acquisition unit that acquires the rectified voltage outputted from the AC power supply input part, an output voltage acquisition unit that acquires the charge voltage outputted from the power conversion part, and a storage part in which the rectified voltage, the charge voltage, and a target intermediate voltage correlated with the rectified voltage and charge voltage are stored.
摘要翻译：充电装置具有对交流电压进行整流的交流电源输入部，将从交流电源输入部输出的整流电压转换为直流中间电压的功率因数校正部，转换输出的中间电压的功率转换部从功率因数校正部变为充电电压，并将充电电压提供给二次电池，获取从交流电源输入部输出的整流电压的输入电压获取单元，获取充电电压的输出电压获取单元以及存储与整流电压和充电电压相关的整流电压，充电电压和目标中间电压的存储部。

10. 发明申请

US20130334879A1 VEHICLE POWER-SUPPLY CONTROL DEVICE 有权
标题翻译：车辆电源控制装置
公开(公告)号：US20130334879A1
公开(公告)日：2013-12-19
申请号：US13917089
申请日：2013-06-13
申请人： Yusaku Ido , Takashi Yamada , Tadao Nishiguchi , Hideyuki Yasugi , Masayuki Hanatani
发明人： Yusaku Ido , Takashi Yamada , Tadao Nishiguchi , Hideyuki Yasugi , Masayuki Hanatani
IPC分类号： B60R16/033
CPC分类号： B60R16/033 , B60L1/00 , B60L1/003 , B60L1/14 , B60L11/1805 , B60L11/1816 , B60L11/1824 , B60L11/1868 , B60L2210/10 , B60L2210/30 , Y02T10/7005 , Y02T10/7066 , Y02T10/7072 , Y02T10/7216 , Y02T10/7241 , Y02T10/92 , Y02T90/121 , Y02T90/127 , Y02T90/14
摘要： A vehicle power-supply control device has a battery charger that converts an externally-supplied AC voltage into a DC voltage used to charge a vehicle high-voltage battery, a low-voltage power generator that converts the DC voltage output from the battery charger into a DC voltage used to drive a vehicle auxiliary machine, and a controller that controls the battery charger and the low-voltage power generator. The battery charger includes a power factor correction circuit that corrects a power factor of the AC voltage and a first DC/DC converter that generates a predetermined DC voltage based on an output of the power factor correction circuit. The low-voltage power generator includes a second DC/DC converter that steps down the DC voltage output from the battery charger and a synchronous rectifier that rectifies an output of the second DC/DC converter in synchronization with a switching operation of the second DC/DC converter.
摘要翻译：车辆电源控制装置具有将外部供给的交流电压转换成用于对车辆用高压电池充电的直流电压的电池充电器，将从电池充电器输出的直流电压转换为低压电力的低压发电机用于驱动车辆辅助机器的DC电压，以及控制电池充电器和低压发电机的控制器。电池充电器包括校正AC电压的功率因数的功率因数校正电路和基于功率因数校正电路的输出产生预定DC电压的第一DC / DC转换器。低压发电机包括：第二DC / DC转换器，其降低从电池充电器输出的直流电压;以及同步整流器，其与第二DC / DC转换器的开关操作同步地整流第二DC / DC转换器的输出; DC转换器。

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