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    • 1. 发明授权
    • Memory access control device and manufacturing method
    • 存储器访问控制装置及其制造方法
    • US08824236B2
    • 2014-09-02
    • US13811482
    • 2012-02-21
    • Takashi MorimotoTakashi Hashimoto
    • Takashi MorimotoTakashi Hashimoto
    • G11C8/00G06F13/00G11C8/04G11C29/00
    • G11C8/04G06F13/00G11C29/00G11C29/022G11C29/4401G11C29/822H01L2224/16225
    • A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
    • 一种存储器访问控制装置,包括:比特位置信息存储单元,存储指示预定长度的比特序列中的一个或多个比特位置的比特位置信息; 读取单元,被配置为尝试从由逻辑地址接收单元接收的逻辑地址指定的范围内读取比特序列,从而以预定长度为单位从外部存储器接收第一比特序列,第一比特序列被组合 的位数大于存储在由逻辑地址指定的范围内的位数; 比特序列提取单元,被配置为以由所述比特位置信息指定的所述一个或多个比特位置以所述预定长度为单位从所述第一比特序列提取一个或多个比特序列。
    • 3. 发明申请
    • MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD
    • 存储器访问控制装置和制造方法
    • US20130121093A1
    • 2013-05-16
    • US13811482
    • 2012-02-21
    • Takashi MorimotoTakashi Hashimoto
    • Takashi MorimotoTakashi Hashimoto
    • G11C8/04
    • G11C8/04G06F13/00G11C29/00G11C29/022G11C29/4401G11C29/822H01L2224/16225
    • A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
    • 一种存储器访问控制装置,包括:比特位置信息存储单元,存储指示预定长度的比特序列中的一个或多个比特位置的比特位置信息; 读取单元,被配置为尝试从由逻辑地址接收单元接收的逻辑地址指定的范围内读取比特序列,从而以预定长度为单位从外部存储器接收第一比特序列,第一比特序列被组合 的位数大于存储在由逻辑地址指定的范围内的位数; 比特序列提取单元,被配置为以由所述比特位置信息指定的所述一个或多个比特位置以所述预定长度为单位从所述第一比特序列提取一个或多个比特序列。