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1. 发明授权

US06667505B2 Semiconductor device having a plurality of capacitors aligned at regular intervals 有权
标题翻译：具有以规则间隔对准的多个电容器的半导体器件
公开(公告)号：US06667505B2
公开(公告)日：2003-12-23
申请号：US10123165
申请日：2002-04-17
申请人： Koichiro Narimatsu , Shigeru Shiratake
发明人： Koichiro Narimatsu , Shigeru Shiratake
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L27/0207 , H01L28/90
摘要： A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.
摘要翻译：半导体器件包括形成为具有大致椭圆形横截面形状并从每个所述存储节点接触件的上表面向上延伸的电容器。当从上方观察电容器的布置时，形成电容器行，使得沿着近似椭圆的长轴的方向，多个电容器以规则的间隔对准。当将所述电容器行中的任意一个作为第一电容器行时，与其并联布置第二电容器行，并且第一电容器行和第二电容器行中的电容器彼此相位相差大约对应的长度到一个传输门的宽度和传输门之间的一个空间的宽度之和。

2. 发明授权

US08669172B2 Method of manufacturing nonvolatile semiconductor device 有权
标题翻译：非易失性半导体器件的制造方法
公开(公告)号：US08669172B2
公开(公告)日：2014-03-11
申请号：US13488015
申请日：2012-06-04
申请人： Yasuaki Yonemochi , Hisakazu Otoi , Akio Nishida , Shigeru Shiratake
发明人： Yasuaki Yonemochi , Hisakazu Otoi , Akio Nishida , Shigeru Shiratake
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/7682 , H01L27/115 , H01L29/42324
摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
摘要翻译：一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分包括电影。由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

3. 发明授权

US08105907B2 Manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的制造方法
公开(公告)号：US08105907B2
公开(公告)日：2012-01-31
申请号：US12696695
申请日：2010-01-29
申请人： Eiji Hasunuma , Shigeru Shiratake , Takeshi Ohgami
发明人： Eiji Hasunuma , Shigeru Shiratake , Takeshi Ohgami
IPC分类号： H01L21/336
CPC分类号： H01L27/10897 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L27/10894
摘要： To provide a manufacturing method of a semiconductor memory device, the method including forming contact plugs to be connected to a drain region or a source region of each of transistors, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having a line-shaped opening provided across the contact plugs. Each of the transistors constituting a sense amplifier that amplifies a potential difference between bit lines is a ring-gate transistor.
摘要翻译：为了提供一种半导体存储器件的制造方法，该方法包括通过使用选择性蚀刻绝缘层的SAC线技术来形成要连接到每个晶体管的漏极区域或源极区域的接触插塞，晶体管通过使用设置在接触插塞两端的具有线状开口的掩模。构成放大位线之间的电位差的读出放大器的晶体管的每一个都是环形栅极晶体管。

4. 发明授权

US06531757B2 Semiconductor device fuse box with fuses of uniform depth 失效
标题翻译：具有均匀深度的保险丝的半导体器件保险丝盒
公开(公告)号：US06531757B2
公开(公告)日：2003-03-11
申请号：US09993954
申请日：2001-11-27
申请人： Shigeru Shiratake
发明人： Shigeru Shiratake
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： A semiconductor device with a fuse box includes at least two gate electrodes 8, 9 and a fuse member 6. The two gate electrodes 8, 9 are formed on at least one insulating film 13 on a semiconductor substrate 100. The fuse member 6 is formed on the insulating film 13 on the semiconductor substrate 100. The two gate electrodes 8, 9 are electrically connected each other by the fuse member 6. In addition, the insulating film 13 and a field region 2 constituted by a semiconductor region are arranged adjacent to each other in a frame-like guard ring 1. The guard ring 1 is constituted by a semiconductor region formed on the semiconductor substrate 100.
摘要翻译：具有保险丝盒的半导体器件包括至少两个栅极电极8,9和熔丝部件6.两个栅极电极8,9形成在半导体衬底100上的至少一个绝缘膜13上。熔丝部件6形成在半导体衬底100上的绝缘膜13上。两个栅极电极8,9通过熔丝部件6彼此电连接。此外，绝缘膜13和由半导体区域构成的场区域2被布置成邻近保护环1由形成在半导体基板100上的半导体区域构成。

5. 发明授权

US5623154A Semiconductor device having triple diffusion 失效
标题翻译：具有三重扩散的半导体器件
公开(公告)号：US5623154A
公开(公告)日：1997-04-22
申请号：US477697
申请日：1995-06-07
申请人： Takaaki Murakami , Kenji Yasumura , Shigeru Shiratake
发明人： Takaaki Murakami , Kenji Yasumura , Shigeru Shiratake
IPC分类号： H01L21/76 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/76
CPC分类号： H01L29/0638 , H01L29/7833
摘要： An isolating/insulating film is formed on the surface of a p.sup.- silicon substrate in an element isolating region. An nMOS transistor having a pair of n-type source/drain regions is formed within an element forming region isolated by the isolating oxide film. A p.sup.+ impurity diffusion region is formed on the p.sup.- silicon substrate in such a manner as to be contacted with the lower surface of the isolating oxide film in the element isolating region and to extend at a specified depth from the surface of the p.sup.- silicon substrate in the element forming region. A p-type impurity diffusion region having a p-type impurity concentration higher than that of the p.sup.- silicon substrate is formed at the side end portion of the isolating oxide film in such a manner as to be contacted with the n-type source/drain region. With this arrangement, it is possible to reduce leakage current caused by the distribution of crystal defects in a depletion layer.
摘要翻译：在元件隔离区域中的p-硅衬底的表面上形成隔离/绝缘膜。在由隔离氧化膜隔离的元件形成区域内形成具有一对n型源极/漏极区域的nMOS晶体管。在p-硅衬底上形成p +杂质扩散区，以便与元件隔离区中的隔离氧化膜的下表面接触，并在p硅表面的特定深度延伸基板在元件形成区域中。在隔离氧化膜的侧端部形成p型杂质浓度高于p硅衬底的p型杂质浓度区域，以与n型源极/ 漏区。通过这种布置，可以减少由耗尽层中的晶体缺陷的分布引起的漏电流。

6. 发明申请

US20070096204A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070096204A1
公开(公告)日：2007-05-03
申请号：US11581346
申请日：2006-10-17
申请人： Shigeru Shiratake
发明人： Shigeru Shiratake
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L27/10897 , H01L27/10876 , H01L27/10894
摘要： A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).
摘要翻译：一种制造半导体器件的方法，其中当两个晶体管形成在同一半导体衬底上时，在沟槽栅极晶体管和具有薄栅绝缘膜的平面晶体管中，简化了工艺并获得了高性能。在外围电路区域PE中的栅极绝缘膜（11s）被保护膜（12）覆盖的状态下，在存储单元区域M中形成栅极沟槽（18），然后形成栅极绝缘膜在外围电路区域PE的栅极绝缘膜（11s）仍然被覆盖的状态下，在栅极沟槽（18）的内壁上形成比栅极绝缘膜（11s）厚的栅极（19）通过保护膜（12）。

7. 发明申请

US20060231884A1 Nonvolatile semiconductor device and method of manufacturing nonvolatile semiconductor device 有权
标题翻译：非易失性半导体器件及制造非易失性半导体器件的方法
公开(公告)号：US20060231884A1
公开(公告)日：2006-10-19
申请号：US11402972
申请日：2006-04-13
申请人： Yasuaki Yonemochi , Hisakazu Otoi , Akio Nishida , Shigeru Shiratake
发明人： Yasuaki Yonemochi , Hisakazu Otoi , Akio Nishida , Shigeru Shiratake
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/7682 , H01L27/115 , H01L29/42324
摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.
摘要翻译：一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在第一浮动栅极和第二浮动栅极之间的间隙部分包括电影。由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

8. 发明授权

US06864546B2 Semiconductor device having memory cell portion and manufacturing method thereof 失效
标题翻译：具有存储单元部分的半导体器件及其制造方法
公开(公告)号：US06864546B2
公开(公告)日：2005-03-08
申请号：US10699890
申请日：2003-11-04
申请人： Takashi Terauchi , Shigeru Shiratake
发明人： Takashi Terauchi , Shigeru Shiratake
IPC分类号： H01L21/8242 , H01L21/8239 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/1052 , H01L27/115 , H01L27/11543
摘要： A semiconductor device having a memory cell portion and a peripheral circuit portion is provided which achieves suppression of reduction of punch-through margin of transistors in the peripheral circuit portion and offers ensured short margin and enhanced current driving capability. After a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to improve burying characteristics after formation of an interlayer insulating film, and also after a high-temperature (800° C. to 1000° C.) thermal treatment that is performed to enhance refresh characteristics after formation of contact plugs in the memory cell portion, a silicon oxide film and insulating film formed on a semiconductor substrate in the peripheral circuit portion are removed by anisotropic dry-etching, leaving the insulating film as sidewall insulating films on sides of sidewall nitride films. Then an impurity ion implantation process is performed using gate interconnections as implant masks to form source/drain regions in the peripheral circuit portion.
摘要翻译：提供了具有存储单元部分和外围电路部分的半导体器件，其实现了抑制外围电路部分中的晶体管的穿通余量的减小，并提供了确保的短边和增强的电流驱动能力。在高温（800℃〜1000℃）的热处理之后，为了提高层间绝缘膜形成后的埋藏特性，以及高温（800℃〜1000℃））通过各向异性干蚀刻除去在存储单元部分中形成接触插塞之后形成接触插塞，形成在外围电路部分中的半导体衬底上的氧化硅膜和绝缘膜上的刷新特性的热处理，留下绝缘膜作为侧壁氮化物膜侧壁上的侧壁绝缘膜。然后使用栅极互连作为注入掩模来执行杂质离子注入工艺，以在外围电路部分中形成源/漏区。

9. 发明授权

US5293508A Ion implanter and controlling method therefor 失效
标题翻译：离子注入机及其控制方法
公开(公告)号：US5293508A
公开(公告)日：1994-03-08
申请号：US865275
申请日：1992-04-08
申请人： Shigeru Shiratake , Hirohisa Yamamoto
发明人： Shigeru Shiratake , Hirohisa Yamamoto
IPC分类号： C23C14/48 , C23C14/54 , C23C30/00 , H01J37/24 , H01J37/317 , H01L21/265 , H05F3/04
CPC分类号： C23C8/36 , H01J37/026 , H01J37/3171 , H01J2237/0042 , H01J2237/0045 , H01J2237/1202 , H01J2237/1215 , H01J2237/20
摘要： An ion implanter encloses a semiconductor substrate adjacent to a fixing member which retains a semiconductor substrate on a supporting bed. The ion implanter includes a ring electrode for generating secondary electrons in response to incident ions and a cup-like electrode for directing the secondary ions to the semiconductor substrate. The ring electrode is negatively biased with respect to the supporting bed and the cup-like electrode surrounds the outer edge of the semiconductor substrate. The ion implanter increases the quantity of the secondary electrons produced and efficiently directs them to the semiconductor substrate. The semiconductor substrate which is electrically charged by implanting ions is neutralized, preventing dielectric breakdown from occurring in an insulating film.
摘要翻译：离子注入机包围与固定部件相邻的半导体衬底，该固定部件将半导体衬底保持在支撑床上。离子注入机包括用于响应于入射离子产生二次电子的环形电极和用于将二次离子引导到半导体衬底的杯形电极。环状电极相对于支撑床呈负偏置，杯形电极围绕半导体衬底的外边缘。离子注入机增加产生的二次电子的量并有效地将它们引导到半导体衬底。通过注入离子而带电的半导体衬底被中和，防止在绝缘膜中发生电介质击穿。

10. 发明授权

US08129770B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08129770B2
公开(公告)日：2012-03-06
申请号：US12687001
申请日：2010-01-13
申请人： Shigeru Shiratake
发明人： Shigeru Shiratake
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/10855 , H01L27/0207 , H01L27/10814 , H01L27/10888 , H01L27/10894
摘要： A semiconductor device includes a silicon substrate having an active region, a memory transistor having a pair of source/drain regions and a gate electrode layer, a hard mask layer on the gate electrode layer having a plane pattern shape identical with that of the gate electrode layer, and plug conductive layers each electrically connected to each of the pair of source/drain regions. An extending direction of the active region is not perpendicular to that of the gate electrode layer, but is oblique. Upper surfaces of the hard mask layer and each of the plug conductive layers form substantially an identical plane. This can attain a semiconductor device allowing significant enlargement of a margin in a photolithographic process, suppression of an “aperture defect” as well as ensuring of a process tolerance of a “short” by decreasing a microloading effect, and decrease in a contact resistance, and a manufacturing method thereof.
摘要翻译：半导体器件包括具有有源区的硅衬底，具有一对源极/漏极区和栅极电极层的存储晶体管，栅电极层上的硬掩模层具有与栅电极的平面图形相同的平面图形层，并且插塞导电层，每个导电层电连接到该对源/漏区中的每一个。有源区的延伸方向不与栅电极层的延伸方向垂直，而是倾斜。硬掩模层和每个插塞导电层的上表面基本上形成相同的平面。这可以获得允许在光刻工艺中显着增大余量的半导体器件，抑制“孔径缺陷”以及通过减小微负载效应来确保“短路”的工艺公差，以及降低接触电阻，及其制造方法。

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