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1. 发明申请

US20120257442A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20120257442A1
公开(公告)日：2012-10-11
申请号：US13463355
申请日：2012-05-03
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.
摘要翻译：具有读字线，写字线和子字驱动器的半导体存储器件，可操作以使用主字信号和反读块信号来选择读字线。子字线使用主字信号和反写写信号来选择写字线。子字驱动器具有使用主字信号作为输入并输出读字线的第一反相器电路。子字驱动器具有分别具有与读取字线连接的漏极，源极和栅极的第一晶体管，低电位电源和反向写入块信号，以及具有漏极的第二晶体管，源极和连接到第一反相器电路的电源端子的栅极，电源和反向写入块信号，并且可以选择写入字线。

2. 发明授权

US08206197B2 Polishing apparatus and program thereof 有权
标题翻译：抛光装置及其程序
公开(公告)号：US08206197B2
公开(公告)日：2012-06-26
申请号：US12596333
申请日：2008-04-17
申请人： Hidetaka Nakao , Masafumi Inoue , Koichi Takeda
发明人： Hidetaka Nakao , Masafumi Inoue , Koichi Takeda
IPC分类号： B24B49/00 , B24B1/00
CPC分类号： H01L21/67219 , B24B37/042 , B24B37/345 , G05B19/41865 , G05B2219/32304 , G05B2219/45232 , H01L21/02074 , H01L21/67276 , Y02P90/20
摘要： A polishing apparatus includes a loading section (14) for placing therein a cassette (12) in which a plurality of polishing objects are housed; a first polishing line (20) and a second polishing line (30) for polishing a polishing object; a cleaning line (40) having cleaning machines (42a, 42b, 42c, 42d) for cleaning the polishing object after polishing and a transport unit (44) for transporting the polishing object; a transport mechanism (50) for transporting the polishing object between the loading section (14), the polishing lines (20, 30) and the cleaning line (40); and a control section for controlling the polishing lines (20, 30), the cleaning line (40) and the transport mechanism (50). The control section determines a polishing start time in each of the first and second polishing lines (20, 30) based on a predicted polishing time in each of the first and second polishing lines (20, 30), a predicted transport time in the transport mechanism (50), a predicted cleaning time in the cleaning line (40) and a predicted cleaning start time to start cleaning by driving the transport unit (44) of the cleaning line (40).
摘要翻译：抛光装置包括用于放置其中容纳有多个抛光对象的盒（12）的装载部（14）; 用于抛光抛光对象的第一抛光线（20）和第二抛光线（30）; 清洁线（40），其具有用于清洁抛光后的抛光对象物的清洁机（42a，42b，42c，42d）和用于输送抛光对象物的输送单元（44）用于在加载部分（14），抛光线（20,30）和清洁线（40）之间传送抛光对象的传送机构（50）; 以及用于控制研磨线（20,30），清洁线（40）和输送机构（50）的控制部。控制部分基于第一和第二研磨线（20,30）中的每一个中的预测的抛光时间来确定第一和第二抛光线（20,30）中的每一个中的抛光开始时间，运送中预测的运送时间机构（50），清洁管线（40）中的预测清洁时间和通过驱动清洗管线（40）的输送单元（44）开始清洁的预测清洁开始时间。

3. 发明授权

US08199594B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08199594B2
公开(公告)日：2012-06-12
申请号：US12910536
申请日：2010-10-22
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C7/00
CPC分类号： G11C11/412
摘要： The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.
摘要翻译： SRAM单元由使用存储节点V2作为输入的反相器电路（P1，N1）和作为输出的存储节点V1，使用存储节点连接在电源VDD与存储节点V2之间的负载晶体管P2 V1作为输入，存储节点V2作为输出，连接在读取位线RBL和存储节点V1之间的存取晶体管N3以及连接在写位线WBL与存储节点V2之间的存取晶体管N4。当访问晶体管N4由写入字线WWL控制时，存取晶体管N4可以用作存储单元的保持控制装置和写入装置，使得可以获得能够以高速操作的半导体器件少数元素。

4. 发明授权

US08164962B2 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US08164962B2
公开(公告)日：2012-04-24
申请号：US12585495
申请日：2009-09-16
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C11/417 , G11C11/419
摘要： A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.
摘要翻译：半导体存储装置包括SRAM电路，其具有存储数据的第一SRAM单元和放大数据的电位差并存储电位差的第二SRAM单元;输出第一控制信号的字线驱动器电路，用于选择第一要读/写数据的SRAM单元和用于选择要读/写电位差的第二SRAM单元之一的第二控制信号，放大从位线对输出的读信号的电位差的读出放大器电路根据第二控制信号选择的第二SRAM单元;以及写入驱动器电路，其将写入信号输出到根据第二控制信号选择的第二SRAM单元的位线对，并且写入信号之间具有电位差，位线大于读取信号。

5. 发明授权

US08134863B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08134863B2
公开(公告)日：2012-03-13
申请号：US12923264
申请日：2010-09-13
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C11/00
CPC分类号： G11C5/025
摘要： A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array.
摘要翻译：根据本发明的半导体器件包括：第一存储单元阵列，其中多个第一存储单元被布置为矩阵，从第一存储单元读取或写入数据;第二存储单元阵列，其中多个放置并存储布置在相应列中的多个第一存储单元之一的数据的第二存储单元被布置为矩阵。第一存储单元阵列和第二存储单元阵列在列方向上面对面布置。第二存储单元的区域大于第一存储单元的区域。第一存储单元阵列的面积是第二存储单元阵列的面积的两倍或更多倍。

6. 发明授权

US07982505B2 Logic circuit, address decoder circuit and semiconductor memory 失效
标题翻译：逻辑电路，地址解码电路和半导体存储器
公开(公告)号：US07982505B2
公开(公告)日：2011-07-19
申请号：US12518793
申请日：2007-12-12
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： H03K19/20 , G11C8/00
CPC分类号： H03K19/0016 , G11C7/22 , G11C7/225 , G11C8/10 , G11C8/18 , G11C2207/2227 , H03K19/20
摘要： Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.
摘要翻译：公开了一种逻辑电路，包括接收第一脉冲信号和第一选择信号的第一NAND门，反相第一NAND门的输出信号以输出结果信号的第一反相器门，接收第二NAND门的第二NAND门脉冲信号和第一选择信号;第二反相器门，反相第二与非门的输出信号;第一PMOS晶体管，漏极端连接到第一与非门的输出;栅极，第二NAND门和连接到电源电压的源极端子，以及第一NMOS晶体管，漏极端子连接到第一反相器栅极的输出，栅极端子连接到第二反相器栅极的输出端，源极端子连接到地下潜力。

7. 发明申请

US20110142231A1 Prime number generating device, prime number generating method, and computer readable storage medium 审中-公开
标题翻译：素数产生装置，素数产生方法和计算机可读存储介质
公开(公告)号：US20110142231A1
公开(公告)日：2011-06-16
申请号：US12926775
申请日：2010-12-08
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： H04L9/30
CPC分类号： G06F7/72 , G06F2207/7204 , H04L9/3033 , H04L2209/56
摘要： A prime number generating device is provided that includes a computation unit capable of performing at least addition and division on data of a predetermined number of bits or less; a prime number candidate data generating unit that generates prime number candidate data with a larger number of bits than the predetermined number of bits; a partitioned prime number candidate data generating unit that generates a plurality of partitioned prime number candidate data elements by partitioning the prime number candidate data; and a determination data generating unit that generates determination data for determining whether or not the prime number candidate expressed by the prime number candidate data is a composite number by using the computation unit to add together the respective plurality of partitioned prime number candidate data elements.
摘要翻译：提供一种质数产生装置，其包括能够至少对预定位数或更少的数据进行加法和除法的计算单元; 素数候选数据生成单元，生成比预定位数大的位数的素数候选数据; 分割素数候选数据生成单元，其通过分割素数候选数据来生成多个分割的素数候选数据元素; 以及确定数据生成单元，其生成用于通过使用所述计算单元来确定由所述素数候选数据表示的素数候选数据是否为合成数量的确定数据，以将相应的多个分割的素数候选数据元素相加在一起。

8. 发明申请

US20110032741A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110032741A1
公开(公告)日：2011-02-10
申请号：US12910536
申请日：2010-10-22
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C7/10 , G11C7/08 , G11C5/06
CPC分类号： G11C11/412
摘要： The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.
摘要翻译： SRAM单元由使用存储节点V2作为输入的反相器电路（P1，N1）和作为输出的存储节点V1，使用存储节点连接在电源VDD与存储节点V2之间的负载晶体管P2 V1作为输入，存储节点V2作为输出，连接在读取位线RBL和存储节点V1之间的存取晶体管N3以及连接在写位线WBL与存储节点V2之间的存取晶体管N4。当访问晶体管N4由写入字线WWL控制时，存取晶体管N4可以用作存储单元的保持控制装置和写入装置，使得可以获得能够以高速操作的半导体器件少数元素。

9. 发明申请

US20100149887A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING POWER SOURCE 有权
标题翻译：半导体存储器件和控制电源的方法
公开(公告)号：US20100149887A1
公开(公告)日：2010-06-17
申请号：US12067265
申请日：2006-09-27
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/147 , G11C11/417
摘要： A voltage generator that monitors a writing margin as a control amount in order to carry out an optimum power source control when control of a SRAM cell power source is carried out at writing operation, and always keeps the writing margin constant; and a power source selector are included to switch power source voltage at writing. By switching the power source voltage at writing, a semiconductor memory device in which a stable writing operation is achieved without largely deteriorating writing time in the SRAM cell and an ultrahigh speed operation or ultralow power operation can be carried out is obtained.
摘要翻译：将写入裕量作为控制量进行监视的电压发生器，以便在写入动作时进行SRAM单元电源的控制时，进行最佳的电源控制，并始终保持写入余量不变; 并且包括电源选择器以在写入时切换电源电压。通过在写入时切换电源电压，可以实现其中实现稳定写入操作而不会使SRAM单元中的写入时间大大恶化以及超高速操作或超低功耗操作的半导体存储器件。

10. 发明授权

US07532536B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07532536B2
公开(公告)日：2009-05-12
申请号：US10577398
申请日：2004-09-17
申请人： Koichi Takeda
发明人： Koichi Takeda
IPC分类号： G11C8/00 , G11C7/10 , G11C11/00
CPC分类号： G11C11/412 , H01L27/11
摘要： The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not accessed, the hold control transistor causes the first and second inverter circuits to form the loop connected hold circuit for statically holding data. When the memory cell is accessed, the hold control transistor causes the first and second inverter circuits to be disconnected from the loop connection for dynamically holding data, thereby preventing data corruption that would otherwise possible occur due to a read operation. Moreover, a sense amplifier circuit that uses a single bit line to read data from a memory cell is disposed in a space appearing in the memory cell array, thereby effectively using the area.
摘要翻译：半导体存储装置的SRAM单元各自包括彼此环路连接的第一和第二反相器电路，以形成保持电路; 两个存取晶体管; 以及与第二反相器电路的驱动晶体管串联连接的保持控制晶体管。当存储单元不被访问时，保持控制晶体管使得第一和第二反相器电路形成用于静态保持数据的环路保持电路。当存储单元被访问时，保持控制晶体管使得第一和第二反相器电路与循环连接断开，用于动态保持数据，从而防止由于读取操作而可能发生的数据损坏。此外，使用单个位线从存储单元读取数据的读出放大器电路设置在出现在存储单元阵列中的空间中，从而有效地使用该区域。

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