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1. 发明授权

US06748037B1 Digital broadcasting receiver 有权
标题翻译：数字广播接收机
公开(公告)号：US06748037B1
公开(公告)日：2004-06-08
申请号：US09554690
申请日：2000-05-18
申请人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matuda
发明人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matuda
IPC分类号： H04L2706
CPC分类号： H04L27/2273 , H04L2027/0057 , H04L2027/0067 , H04L2027/0077 , H04L2027/0095
摘要： A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit (6) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit (92) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit (94) calculates the polarity of the error frequency. A step frequency control circuit (96) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.
摘要翻译：提供一种数字广播接收机，其可以快速地再现载波并以高速捕获期望的信号。载波再现相位误差检测电路（6）根据在标题部分中的预定部分期间解调调制波的解调波得到的解调输出来检测相位误差电压。峰值计算电路（92）根据相位误差电压计算期望的接收频率和再现载波频率之间的误差频率。差分系数计算电路（94）计算误差频率的极性。步进频率控制电路（96）将计算出的极性的计算误差频率转换为用于自动频率控制的步进频率宽度。以转换的步进频率宽度扫描再现载波频率，直到在检测到帧同步之后建立帧同步。因此，可以快速地再现载体并以高速捕获期望的信号。

2. 发明授权

US06700940B1 Carrier reproduction circuit 有权
标题翻译：载波再现电路
公开(公告)号：US06700940B1
公开(公告)日：2004-03-02
申请号：US09581212
申请日：2000-08-15
申请人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
发明人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
IPC分类号： H04B1700
CPC分类号： H04L27/2273
摘要： A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.
摘要翻译：提供即使在以低C / N值进行接收的情况下也能够执行稳定的载波再现的载波再现电路。利用帧同步定时电路（4）检测解调的已知模式接收信号的接收相位，并且基于检测到的接收相位，具有一个收敛点的绝对相位的相位差表或者具有一个收敛点的相位差表选择包含在载波再现相位差检测电路（8）中的从绝对相位旋转180°的相位，并且从所选择的相位差表中选择基于从信号点获得的相位之间的相位差的输出获得接收信号和相位收敛点的位置，从而通过经由AFC电路（10）经历再现的载波频率控制来实现载波再现，使得从信号点位置获得的相位与相位收敛点一致。

3. 发明授权

US06678336B1 Hierarchical transmission digital demodulator 有权
标题翻译：分层传输数字解调器
公开(公告)号：US06678336B1
公开(公告)日：2004-01-13
申请号：US09554669
申请日：2000-08-09
申请人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda
发明人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda
IPC分类号： H04L2706
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0057 , H04L2027/0081 , H04L2027/0095
摘要： A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.
摘要翻译：一种能够通过根据接收C / N值设置解调操作来稳定同步捕获和稳定解调的分级发送数字解调器。 CNR测量电路从运算电路接收解调输出并测量接收C / N值。在捕获同步之前的一段时间内，根据解调输出再现载波，以便在报头部分中的调制波和突发符号信号的调制波。在捕获同步之后，以中间C / N值，根据标题部分的解调输出，突发符号信号和QPSK信号，并根据逻辑门电路的输出，以及在高和低C / N值通过根据来自逻辑门电路的信号设置增益控制电路的载波再生环路增益来重放载波。

4. 发明授权

US06639951B1 Digital demodulator 有权
标题翻译：数字解调器
公开(公告)号：US06639951B1
公开(公告)日：2003-10-28
申请号：US09554689
申请日：2000-05-18
申请人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
发明人： Hisakazu Katoh , Akinori Hashimoto , Tomohiro Saito , Fumiaki Minematsu , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
IPC分类号： H04L2714
CPC分类号： H04L27/2332 , H04L7/04 , H04L2027/003 , H04L2027/0057 , H04L2027/0095
摘要： A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter (7) according to an inversion command signal “0” or “1” that is output from an inversion decision circuit (6) depending on a BPSK signal of a known pattern. A phase error detector (8) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter (7). The phase error voltage is passed through a carrier filter (9), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.
摘要翻译：提供了一种无需绝对相位电路的数字解调器。在用于数字广播接收机的数字解调器中，接收不同类型调制的数字时分多路复用信号，根据反相器（7）根据反相指令信号“0”或“1”选择性地将解调的基带信号反相，根据已知图案的BPSK信号从反转判定电路（6）输出。用于载波再现的相位误差检测器（8）基于从逆变器（7）输出的解调的基带信号的信号点的绝对相位和相位之间的相位差来确定相位误差电压。相位误差电压通过包括低通滤波器的载波滤波器（9），以控制载波频率，使得载波再现可以在信号点处的相位与相位收敛点一致。

5. 发明授权

US06813321B1 Digital demodulator 有权
标题翻译：数字解调器
公开(公告)号：US06813321B1
公开(公告)日：2004-11-02
申请号：US09582229
申请日：2000-07-21
申请人： Hisakazu Katoh , Akinori Hashimoto , Yuichi Iwadate , Kazuhiko Shibuya , Fumiaki Minematsu , Shigeyuki Itoh , Tomohiro Saito , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
发明人： Hisakazu Katoh , Akinori Hashimoto , Yuichi Iwadate , Kazuhiko Shibuya , Fumiaki Minematsu , Shigeyuki Itoh , Tomohiro Saito , Kenichi Shiraishi , Akihiro Horii , Shoji Matsuda , Soichi Shinjo
IPC分类号： H03D322
CPC分类号： H04L27/2273 , H04L7/042 , H04L27/0014 , H04L2027/0057 , H04L2027/0067 , H04L2027/0077 , H04L2027/0095
摘要： A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit 6 generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit 7 has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter 8 according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit 6, the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.
摘要翻译：提供了不需要绝对定相电路的数字解调器。已知模式BPSK信号发生电路6与接收的数字调制波中的已知模式BPSK信号同步地产生与接收的数字调制波中已知模式BPSK信号相同的已知模式BPSK信号，载波再现相位误差检测电路7具有相位误差表，其中解调基带信号的信号点位置中的参考相位之一成为会聚点，相位误差电压对应于从信号点位置确定的相位之间的相位误差通过根据从已知模式BPSK信号发生电路6输出的已知模式BPSK信号启用控制载波再现环路滤波器8，发送解调基带信号和相位收敛点，平滑相位误差电压并且在根据平滑输出控制再现载波的频率的同时执行载波再现，使得si中的相位点位置与相位收敛点一致。

6. 发明授权

US06526107B1 Synchronization acquiring circuit 失效
标题翻译：同步采集电路
公开(公告)号：US06526107B1
公开(公告)日：2003-02-25
申请号：US09530962
申请日：2000-07-12
申请人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii
发明人： Hisakazu Katoh , Akinori Hashimoto , Kenichi Shiraishi , Akihiro Horii
IPC分类号： H04L700
CPC分类号： H04J3/0605 , H04J3/0608 , H04L7/0083 , H04L27/22
摘要： There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit 2. The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit 5 to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.
摘要翻译：提供了一种在低C / N时接收帧同步时稳定地获取帧同步而不进行伪同步锁定的同步获取电路。接收帧的同步模式由帧同步检测电路2检测。通过帧同步电路5将接收帧的同步模式的比特与发送侧的帧同步模式的位进行比较，以获得数字一致的位。当获得的每帧的比特数等于或大于相关检测值时，认为帧同步被检测。

7. 发明授权

US06772378B1 Dummy error addition circuit 失效
标题翻译：虚假误差加法电路
公开(公告)号：US06772378B1
公开(公告)日：2004-08-03
申请号：US09807029
申请日：2001-04-09
申请人： Kenichi Ishihara , Kenichi Shiraishi , Soichi Shinjo , Akihiro Horii
发明人： Kenichi Ishihara , Kenichi Shiraishi , Soichi Shinjo , Akihiro Horii
IPC分类号： G06F1100
CPC分类号： H04L1/00 , H04L1/0003 , H04L1/241
摘要： A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.
摘要翻译：一种用于向正交调制符号数据添加虚拟错误的虚拟错误添加电路，其中基于指定的误码率的值被加载以对计数器（11）计数时钟信号，计数器（11）的载波存储输出当存储与计数器（11）的计数值一致的数据被识别为误差脉冲时，从PN比较电路（3）输出来自移位寄存器（22）中的PN数据发生器（21）的位选择器（40）在接收到错误脉冲并基于PN数据生成器（41）的输出时，随机地选择在正交调制数据中添加错误的位，例如基于比特误码率的间隔的PSK调制符号数据和从正交调制数据中选择的比特在比特反相电路（5）中反转，从而输出错误。

8. 发明授权

US06748033B1 De-interleave circuit 有权
标题翻译：去交错电路
公开(公告)号：US06748033B1
公开(公告)日：2004-06-08
申请号：US09743718
申请日：2001-01-16
申请人： Kenichi Shiraishi , Soichi Shinjo , Akihiro Horii
发明人： Kenichi Shiraishi , Soichi Shinjo , Akihiro Horii
IPC分类号： H04L2706
CPC分类号： H03M13/276 , H03M13/2735 , H03M13/2785
摘要： To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a de-interleave memory (4) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory (4) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory (4) only requires space for one superframe.
摘要翻译：提供用于BS数字广播接收机的解交织电路。解交织电路具有较少的存储器。地址数据生成器（3）以去交织顺序将地址数据（A）提供给解交织存储器（4）。从由地址数据（A）指定的解交织存储器（4）中的地址位置读取每个主信号，并且将以下主信号交织并写入存储器的该地址位置。结果，解交织存储器（4）仅需要一个超帧的空间。

9. 发明授权

US06714596B1 BS digital broadcast receiver 有权
标题翻译： BS数字广播接收机
公开(公告)号：US06714596B1
公开(公告)日：2004-03-30
申请号：US09582228
申请日：2000-07-21
申请人： Kenichi Shiraishi , Akihiro Horii , Soichi Shinjo , Shoji Matsuda , Ryuichi Okazaki
发明人： Kenichi Shiraishi , Akihiro Horii , Soichi Shinjo , Shoji Matsuda , Ryuichi Okazaki
IPC分类号： H04L2302
CPC分类号： H04L1/0052 , H04L1/0054 , H04L1/006 , H04L27/2332 , H04L2027/0032 , H04L2027/0057
摘要： A BS digital broadcast receiver having no 8PSK-demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder 6. An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder 7. Upper four bits of phase error data are searched from a phase error table 31 for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits 81 to 84 by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit 9. A code TCD2 determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit 10.
摘要翻译：没有8PSK解映射器的BS数字广播接收机和用于网格编码的较少数量的延迟电路。基于绝对相位基带解调信号的接收信号点位置的QPSK基带信号由维特比解码器6进行维特比解码。维特比解码器的输出由卷积编码器7进行卷积重新编码。高四位根据0度与相位误差检测接收信号点位置的相位之间的相位差，从用于载波再现的相位误差表31中搜索相位误差数据。延迟电路81至84通过维特比解码所花费的时间和对卷积编码所花费的时间的总和来延迟高四位。延迟的输出被去映射值转换电路9解映射。从解映射的输出和卷积编码输出确定的代码TCD2作为从MSB代码判断/错误检测电路10的格状8PSK解码输出的MSB输出。

10. 发明授权

US06683921B1 Received-signal absolute phasing apparatus of receiver 有权
标题翻译：接收机的接收信号绝对定相装置
公开(公告)号：US06683921B1
公开(公告)日：2004-01-27
申请号：US09581509
申请日：2000-06-16
申请人： Kenichi Shiraishi , Akihiro Horii
发明人： Kenichi Shiraishi , Akihiro Horii
IPC分类号： H03D322
CPC分类号： H04L27/22 , H04L27/2273
摘要： When reception of a multiplexed wave to be PSK-modulated of BPSK, QPSK, and 8PSK is started, a selector (16A) of a demodulating circuit (1A) reads high-order three bits &Dgr;&phgr;(3) of phase error data corresponding to I and Q symbol streams out of one phase error table (15-1) for BPSK among phase error tables provided for each modulation system and each phase rotation angle. A received-signal-phase rotation angle detecting circuit (8A) detects phase rotation angles of portions corresponding to bits (1) and (0) of a frame-synchronizing signal of a received symbol stream from the &Dgr;&phgr;(3) and the MSB of I symbol stream and outputs the phase rotation angles to a remapper (7) to make the remapper perform absolute phasing. The selector (16A) reads phase error data corresponding to a received symbol stream out of a phase error table corresponding to a modulation system and a phase rotation angle identified by a transmission-configuration identifying circuit (9), outputs the phase error data to a D/A converter (17), corrects a phase of a reference carrier wave for orthogonal detection, and makes a received-signal point become a constant phase for a transmitted-signal point.
摘要翻译：当接收到对BPSK，QPSK和8PSK进行PSK调制的复用波开始时，解调电路（1A）的选择器（16A）读取对应于I的相位误差数据的高阶三位Deltaphi（3）和用于每个调制系统提供的相位误差表和每个相位旋转角度的BPSK的一个相位误差表（15-1）中的Q个符号流。接收信号相位旋转角度检测电路（8A）检测来自Deltaphi（3）的接收符号流的帧同步信号的与位（1）和（0）相对应的部分的相位旋转角，并且 I符号流并将相位旋转角度输出到再映射器（7），以使再映射器执行绝对定相。选择器（16A）从对应于由发送配置识别电路（9）识别的调制系统和相位旋转角度的相位误差表读出与接收到的符号流相对应的相位误差数据，将相位误差数据输出到 D / A转换器（17），校正用于正交检测的参考载波的相位，并且使接收信号点成为发送信号点的恒定相位。

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