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1. 发明授权

US07127598B2 Semiconductor device comprising transition detecting circuit and method of activating the same 有权
标题翻译：包括转换检测电路的半导体器件及其激活方法
公开(公告)号：US07127598B2
公开(公告)日：2006-10-24
申请号：US10322587
申请日：2002-12-19
申请人： Kohei Oikawa , Shinichiro Shiratake , Yoshiaki Takeuchi , Daisaburo Takashima , Thomas Roehr
发明人： Kohei Oikawa , Shinichiro Shiratake , Yoshiaki Takeuchi , Daisaburo Takashima , Thomas Roehr
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.
摘要翻译：半导体器件包括内部电源，至少一个半导体电路块，延迟电路和检测电路。初始化时，内部电源输出初始化完成信号。半导体电路块基于由内部电源产生的电压进行工作。延迟电路延迟初始化完成信号。检测电路响应于由延迟电路延迟的初始化完成信号和外部输入的第一输入信号，命令半导体电路块开始操作。

2. 发明授权

US06901026B2 Semiconductor integrated circuit equipment with asynchronous operation 失效
标题翻译：具有异步操作的半导体集成电路设备
公开(公告)号：US06901026B2
公开(公告)日：2005-05-31
申请号：US10366418
申请日：2003-02-14
申请人： Yoshiaki Takeuchi , Shinichiro Shiratake , Kohei Oikawa
发明人： Yoshiaki Takeuchi , Shinichiro Shiratake , Kohei Oikawa
IPC分类号： G11C8/06 , G11C8/18 , G11C11/22 , G11C11/403 , G11C11/406 , G11C11/408 , G11C8/00
CPC分类号： G11C11/40615 , G11C8/06 , G11C8/18 , G11C11/22 , G11C11/406
摘要： A semiconductor integrated circuit device includes a memory, /CE transition detector, address transition detector, /WE transition detector and controller. The controller includes a timeout circuit. The timeout circuit generates an internal circuit control signal with preset width to control access to the memory based on detection results of the above transition detectors. The operation of the memory is controlled by the timeout circuit at the read time. The operation of the memory is controlled by the timeout circuit when transition of the end of a /WE signal is detected by the /WE transition detector before a timing specified by the timeout circuit at the write time. Further, the operation of the memory is controlled in response to the transition of the /WE signal when the transition of the end of the /WE signal is detected by the /WE transition detector after passage of the above timing.
摘要翻译：半导体集成电路器件包括存储器/ CE转换检测器，地址转换检测器，/ WE转换检测器和控制器。控制器包括一个超时电路。超时电路根据上述转换检测器的检测结果生成具有预设宽度的内部电路控制信号，以控制对存储器的访问。存储器的操作由读取时的超时电路控制。当在写入时间由超时电路指定的定时之前，由/ WE转换检测器检测到/ WE信号的结束的转换时，存储器的操作由超时电路控制。此外，当在上述定时经过之后，当/ WE信号的结束的转变被/ WE转换检测器检测到时，响应于/ WE信号的转变来控制存储器的操作。

3. 发明授权

US07057917B2 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor 失效
标题翻译：具有耦合到电容器的本征存取晶体管的铁电存储器
公开(公告)号：US07057917B2
公开(公告)日：2006-06-06
申请号：US10743906
申请日：2003-12-24
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器，以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

4. 发明授权

US07295456B2 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor 有权
标题翻译：具有与铁电电容器并联连接的本征晶体管的链式铁电随机存取存储器（CFRAM）
公开(公告)号：US07295456B2
公开(公告)日：2007-11-13
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

5. 发明申请

US20060193162A1 Ferroelectric Memory and Semiconductor Memory 有权
标题翻译：铁电存储器和半导体存储器
公开(公告)号：US20060193162A1
公开(公告)日：2006-08-31
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

6. 发明授权

US06552922B2 Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a sense amplifier and a bit line pair 有权
标题翻译：具有耦合在读出放大器和位线对之间的重写晶体管的链式铁电随机存取存储器（FRAM）
公开(公告)号：US06552922B2
公开(公告)日：2003-04-22
申请号：US10228067
申请日：2002-08-27
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

7. 发明授权

US06473330B1 Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and an equalization circuit 有权
标题翻译：链式铁电存储器，其具有耦合在读出放大器和均衡电路之间的隔离晶体管
公开(公告)号：US06473330B1
公开(公告)日：2002-10-29
申请号：US09585081
申请日：2000-06-01
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

8. 发明申请

US20080285327A1 Ferroelectric Memory and Semiconductor Memory 审中-公开
标题翻译：铁电存储器和半导体存储器
公开(公告)号：US20080285327A1
公开(公告)日：2008-11-20
申请号：US11934399
申请日：2007-11-02
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22 , G11C11/401
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

9. 发明授权

US06671200B2 Ferroelectric random access memory with isolation transistors coupled between a sense amplifier and an equalization circuit 有权
标题翻译：铁电随机存取存储器，其隔离晶体管耦合在读出放大器和均衡电路之间
公开(公告)号：US06671200B2
公开(公告)日：2003-12-30
申请号：US10372886
申请日：2003-02-26
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier, and that a value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管，并且作为栅极电压的最小值在板线电压升高和比较放大期间获得的晶体管的晶体管小于作为板线电压下降期间获得的晶体管中的栅极电压的最大值和比较放大的值。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

10. 发明授权

US07002871B2 Asynchronous pseudo SRAM and access method therefor 失效
标题翻译：异步伪SRAM及其访问方法
公开(公告)号：US07002871B2
公开(公告)日：2006-02-21
申请号：US10762459
申请日：2004-01-23
申请人： Yoshiaki Takeuchi , Kohei Oikawa
发明人： Yoshiaki Takeuchi , Kohei Oikawa
IPC分类号： G11C8/00
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes an address buffer which receives an address signal that indicates an address of a memory cell array, a latch circuit which latches the data, and an address transition detection circuit which detects transition of the address. During the access operation of the memory cell array, an address at the operation start time is latched by the latch circuit. After the end of the operation of the memory cell array, an address that is currently input to the address buffer is latched by the latch circuit. If the received address signal is data different from the latch data, a control signal that controls the cycle operation of the memory cell array for a predetermined period is generated on the basis of the detection result from the address transition detection circuit.
摘要翻译：半导体集成电路装置包括地址缓冲器，其接收指示存储单元阵列的地址的地址信号，锁存数据的锁存电路以及检测地址的转换的地址转换检测电路。在存储单元阵列的访问操作期间，操作开始时刻的地址被锁存电路锁存。在存储单元阵列的操作结束之后，当前输入到地址缓冲器的地址被锁存电路锁存。如果接收到的地址信号是与锁存数据不同的数据，则根据来自地址转换检测电路的检测结果生成控制存储单元阵列的周期操作达预定周期的控制信号。

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