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1. 发明授权

US07127598B2 Semiconductor device comprising transition detecting circuit and method of activating the same 有权
标题翻译：包括转换检测电路的半导体器件及其激活方法
公开(公告)号：US07127598B2
公开(公告)日：2006-10-24
申请号：US10322587
申请日：2002-12-19
申请人： Kohei Oikawa , Shinichiro Shiratake , Yoshiaki Takeuchi , Daisaburo Takashima , Thomas Roehr
发明人： Kohei Oikawa , Shinichiro Shiratake , Yoshiaki Takeuchi , Daisaburo Takashima , Thomas Roehr
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.
摘要翻译：半导体器件包括内部电源，至少一个半导体电路块，延迟电路和检测电路。初始化时，内部电源输出初始化完成信号。半导体电路块基于由内部电源产生的电压进行工作。延迟电路延迟初始化完成信号。检测电路响应于由延迟电路延迟的初始化完成信号和外部输入的第一输入信号，命令半导体电路块开始操作。

2. 发明授权

US07016216B2 Ferroelectric memory device having ferroelectric capacitor and method of reading out data therefrom 失效
标题翻译：具有铁电电容器的铁电存储器件和从其读出数据的方法
公开(公告)号：US07016216B2
公开(公告)日：2006-03-21
申请号：US10680394
申请日：2003-10-08
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes memory cells, a memory cell block, a sense amplifier, a precharge circuit, a bit line drive circuit, and a plate line drive circuit. Each of the memory cells has a cell transistor and a ferroelectric capacitor in between a source and drain of the cell transistor. The memory cell block includes the memory cells that are series connected between a bit line via a block select transistor and a plate line. The sense amplifier amplifies data read out from the memory cell, and generates one of a first potential and a second potential higher than the first potential in accordance with the read-out data. The precharge circuit precharges the bit line at a third potential that is higher than the first potential and lower than the second potential. The bit line drive circuit sets the bit line at a fourth potential.
摘要翻译：铁电存储器件包括存储单元，存储单元块，读出放大器，预充电电路，位线驱动电路和板线驱动电路。每个存储单元在单元晶体管的源极和漏极之间具有单元晶体管和铁电电容器。存储单元块包括串联连接在经由块选择晶体管的位线和板线之间的存储单元。读出放大器放大从存储单元读出的数据，根据读出的数据产生高于第一电位的第一电位和第二电位中的一个。预充电电路在比第一电位高且低于第二电位的第三电位预充电位线。位线驱动电路将位线设置为第四个电位。

3. 发明授权

US06765831B2 Semiconductor integrated circuit device 失效
公开(公告)号：US06765831B2
公开(公告)日：2004-07-20
申请号：US10428763
申请日：2003-05-05
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C800
CPC分类号： G11C11/22
摘要： A semiconductor integrated circuit device includes a memory array, address buffer, address decoder, and controller. The memory array includes a memory cell array in which destructive read-out memory cells are integrated. The address buffer outputs an internal address signal corresponding to an input external address signal. The address decoder decodes the internal address signal and outputs a memory cell selection signal on the basis of the decode result. The controller parallel-executes wait processing of keeping the address buffer in a wait state until the lapse of a skew time after transition of the external address signal is detected, and decode processing until the memory cell selection signal changes from an invalid state to a valid state in response to output of the internal address signal.

4. 发明授权

US06744302B2 Voltage generator circuit for use in a semiconductor device 有权
标题翻译：用于半导体器件的电压发生器电路
公开(公告)号：US06744302B2
公开(公告)日：2004-06-01
申请号：US10310053
申请日：2002-12-05
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G05F110
CPC分类号： G05F3/24
摘要： A voltage generator circuit generates a voltage supplied to an internal circuit. The voltage generator circuit includes first, second, and third switching elements each having first and second terminals. The first terminal of each of the switching elements is connected to the power source terminal supplied with a power source voltage. First, second, and third transistors each have a current path which has first and second ends. The first ends of the first, second, and third transistors are respectively connected to the second terminals of the first, second, and third switching elements. The first, second, and third transistors have respectively first, second, and third driving capabilities. The first, second, and third driving capabilities are different from each other. The second ends of the current paths of the first, second, and third transistors are connected to an output terminal which outputs the voltage supplied to the internal circuit.
摘要翻译：电压发生器电路产生提供给内部电路的电压。电压发生器电路包括具有第一和第二端子的第一，第二和第三开关元件。每个开关元件的第一端子连接到被提供有电源电压的电源端子。第一，第二和第三晶体管各自具有第一和第二端的电流路径。第一，第二和第三晶体管的第一端分别连接到第一，第二和第三开关元件的第二端子。第一，第二和第三晶体管分别具有第一，第二和第三驱动能力。第一，第二和第三驾驶能力彼此不同。第一，第二和第三晶体管的电流路径的第二端连接到输出提供给内部电路的电压的输出端子。

5. 发明授权

US06901026B2 Semiconductor integrated circuit equipment with asynchronous operation 失效
标题翻译：具有异步操作的半导体集成电路设备
公开(公告)号：US06901026B2
公开(公告)日：2005-05-31
申请号：US10366418
申请日：2003-02-14
申请人： Yoshiaki Takeuchi , Shinichiro Shiratake , Kohei Oikawa
发明人： Yoshiaki Takeuchi , Shinichiro Shiratake , Kohei Oikawa
IPC分类号： G11C8/06 , G11C8/18 , G11C11/22 , G11C11/403 , G11C11/406 , G11C11/408 , G11C8/00
CPC分类号： G11C11/40615 , G11C8/06 , G11C8/18 , G11C11/22 , G11C11/406
摘要： A semiconductor integrated circuit device includes a memory, /CE transition detector, address transition detector, /WE transition detector and controller. The controller includes a timeout circuit. The timeout circuit generates an internal circuit control signal with preset width to control access to the memory based on detection results of the above transition detectors. The operation of the memory is controlled by the timeout circuit at the read time. The operation of the memory is controlled by the timeout circuit when transition of the end of a /WE signal is detected by the /WE transition detector before a timing specified by the timeout circuit at the write time. Further, the operation of the memory is controlled in response to the transition of the /WE signal when the transition of the end of the /WE signal is detected by the /WE transition detector after passage of the above timing.
摘要翻译：半导体集成电路器件包括存储器/ CE转换检测器，地址转换检测器，/ WE转换检测器和控制器。控制器包括一个超时电路。超时电路根据上述转换检测器的检测结果生成具有预设宽度的内部电路控制信号，以控制对存储器的访问。存储器的操作由读取时的超时电路控制。当在写入时间由超时电路指定的定时之前，由/ WE转换检测器检测到/ WE信号的结束的转换时，存储器的操作由超时电路控制。此外，当在上述定时经过之后，当/ WE信号的结束的转变被/ WE转换检测器检测到时，响应于/ WE信号的转变来控制存储器的操作。

6. 发明授权

US07154766B2 Ferroelectric memory 有权
公开(公告)号：US07154766B2
公开(公告)日：2006-12-26
申请号：US10934358
申请日：2004-09-07
申请人： Kohei Oikawa , Daisaburo Takashima
发明人： Kohei Oikawa , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/42 , G11C7/00 , G11C7/02 , G11C8/00 , G11C8/18
CPC分类号： G11C11/22
摘要： An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.

7. 发明申请

US20060018144A1 Ferroelectric memory 有权
标题翻译：铁电存储器
公开(公告)号：US20060018144A1
公开(公告)日：2006-01-26
申请号：US10934358
申请日：2004-09-07
申请人： Kohei Oikawa , Daisaburo Takashima
发明人： Kohei Oikawa , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.
摘要翻译：本发明的一个方面提供一种铁电存储器，其包括具有多个串联连接的单位单元的单元块，所述单元块的一端连接到板线，并且所述单元块的另一端连接到位线通过块选择晶体管，连接到位线的读出放大器和控制块选择晶体管的导通/截止的块选择器解码器。用于操作读出放大器和块选择器解码器的定时对应于用于多个单位单元的数据读取的所选择的单位单元目标的位置而改变。

8. 发明授权

US07053696B2 Semiconductor device with resistor element 失效
标题翻译：具有电阻元件的半导体器件
公开(公告)号：US07053696B2
公开(公告)日：2006-05-30
申请号：US10685490
申请日：2003-10-16
申请人： Shinichiro Shiratake , Kohei Oikawa
发明人： Shinichiro Shiratake , Kohei Oikawa
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/565 , H01L29/8605
摘要： A semiconductor device includes first, second, third and fourth resistor elements. The first to fourth resistor elements have first ends commonly connected to a first node, and operate in one of first and second operation modes which are switchable. The first and second resistor elements have second ends connected to a second node and a third node, respectively. The third and fourth resistor elements have second ends connected to a fourth node and a fifth node via a first switch and a second switch, respectively. The first and second switches are opened in the first operation mode, and are closed in the second operation mode.
摘要翻译：半导体器件包括第一，第二，第三和第四电阻器元件。第一至第四电阻器元件具有共同连接到第一节点的第一端，并且可操作为可切换的第一和第二操作模式之一。第一和第二电阻元件分别具有连接到第二节点和第三节点的第二端。第三和第四电阻器元件具有分别经由第一开关和第二开关连接到第四节点和第五节点的第二端。第一和第二开关在第一操作模式下打开，并且在第二操作模式中被关闭。

9. 发明申请

US20060181339A1 Semiconductor device with resistor element 审中-公开
公开(公告)号：US20060181339A1
公开(公告)日：2006-08-17
申请号：US11401303
申请日：2006-04-11
申请人： Shinichiro Shiratake , Kohei Oikawa
发明人： Shinichiro Shiratake , Kohei Oikawa
IPC分类号： G05F1/10
CPC分类号： G05F1/565 , H01L29/8605
摘要： A semiconductor device includes first, second, third and fourth resistor elements. The first to fourth resistor elements have first ends commonly connected to a first node, and operate in one of first and second operation modes which are switchable. The first and second resistor elements have second ends connected to a second node and a third node, respectively. The third and fourth resistor elements have second ends connected to a fourth node and a fifth node via a first switch and a second switch, respectively. The first and second switches are opened in the first operation mode, and are closed in the second operation mode.

10. 发明授权

US06744305B2 Power supply circuit having value of output voltage adjusted 有权
标题翻译：电源电路的输出电压值调整
公开(公告)号：US06744305B2
公开(公告)日：2004-06-01
申请号：US10233529
申请日：2002-09-04
申请人： Kohei Oikawa , Shinichiro Shiratake
发明人： Kohei Oikawa , Shinichiro Shiratake
IPC分类号： G05F146
CPC分类号： G05F1/56
摘要： A power supply circuit includes a transistor, a variable resistance circuit, a second resistance, and an operational amplifier. The variable resistance circuit includes a plurality of first resistances. The plurality of first resistances are selected in response to control signals. The selected first resistances are connected in series with the transistor, the unselected first resistances are connected to a ground voltage. The second resistance is connected between the variable resistance circuit and the ground voltage. The operational amplifier compares a voltage of the one end of the variable resistance circuit with a reference voltage and feeds a signal indicating a comparison result back to the gate of the transistor.
摘要翻译：电源电路包括晶体管，可变电阻电路，第二电阻和运算放大器。可变电阻电路包括多个第一电阻。响应于控制信号选择多个第一电阻。所选择的第一电阻与晶体管串联连接，未选择的第一电阻连接到接地电压。第二电阻连接在可变电阻电路和接地电压之间。运算放大器将可变电阻电路的一端的电压与参考电压进行比较，并将表示比较结果的信号反馈回晶体管的栅极。

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