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1. 发明授权

US5497349A Dynamic random access memory device having first and second I/O line groups isolated from each other 失效
标题翻译：具有彼此隔离的第一和第二I / O线路组的动态随机存取存储器件
公开(公告)号：US5497349A
公开(公告)日：1996-03-05
申请号：US267025
申请日：1994-06-21
申请人： Kiyoshi Nakai , Yukihide Suzuki , Takashi Inui
发明人： Kiyoshi Nakai , Yukihide Suzuki , Takashi Inui
IPC分类号： H01L27/10 , G11C7/10 , G11C11/401 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4096 , G11C7/10
摘要： A dynamic random access memory device has a memory cell array which includes a first memory cell array part and a second memory cell array part portioned in a first direction parallel with the bit lines, a plurality of column switches, one provided for each of the bit lines, a plurality of input/output lines each connected to different ones of the bit lines via associated ones of the column switches, a row address decoder for decoding a first portion of an address signal and a column address decoder for decoding a second portion of the address signal to thereby simultaneously access at least two memory cells with the address signal. The input/output lines extend in a second direction parallel with word lines and are divided into first and second groups of input/output lines connected to those bit lines which belong to the first and second memory cell array parts, respectively in which the first input/output line group is isolated from the second input/output line group. A first input/output gate circuit is connected to the first group of input/output lines and a second input/output gate circuit is connected to the second group of input/output lines, in which the first and second input/output gate circuits serve to selectively transfer therethrough, between main amplifiers and the first input/output line groups, data to be simultaneously read from or written into the at least two memory cells in the memory cell array.
摘要翻译：动态随机存取存储器件具有存储单元阵列，其包括第一存储单元阵列部分和与位线平行的第一方向上分配的第二存储单元阵列部分，多个列开关，每个位开关线路，多个输入/输出线路，每条线路经由相关联的列开关连接到不同的位线，用于解码地址信号的第一部分的行地址解码器和用于解码第二部分的列地址解码器由此地址信号由此同时访问具有地址信号的至少两个存储单元。输入/输出线在与字线平行的第二方向上延伸，并且被分成连接到属于第一和第二存储单元阵列部分的那些位线的第一和第二组输入/输出线，其中第一输入 /输出线路组与第二个输入/输出线组隔离。第一输入/输出门电路连接到第一组输入/输出线，并且第二输入/输出门电路连接到第二组输入/输出线，其中第一和第二输入/输出门电路服务以在主放大器和第一输入/输出线组之间选择性地传送数据，以同时从存储单元阵列中的至少两个存储单元中读取或写入数据。

2. 发明授权

US5557580A Word line driving circuit 失效
标题翻译：字线驱动电路
公开(公告)号：US5557580A
公开(公告)日：1996-09-17
申请号：US292452
申请日：1994-08-18
申请人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
发明人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
IPC分类号： G11C11/407 , G11C8/08 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C8/00 , G11C7/00
CPC分类号： G11C8/08
摘要： A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.
摘要翻译：一种字线驱动电路，通过使字线驱动器的布局面积小，能够有效地防止字线放电期间的接地噪声，同时容纳字线中的音调变窄。字线驱动电路包括n型MOS晶体管14和p型MOS晶体管12. n型MOS晶体管14的漏极端子和字线驱动器10中的p型MOS晶体管12的漏极端子连接到基极字线WLi的终端。输出晶体管驱动电路16的输出端子与p型MOS晶体管12的源极端子连接，第一输出晶体管控制电路18的输出端子与栅极端子连接。第二输出晶体管控制电路20的输出端子与n型MOS晶体管14的栅极端子连接，作为引导电流的基准电位端子的接地端子22与源极端子连接。

3. 发明授权

US5615156A Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines 失效
标题翻译：半导体存储器件具有多个具有中心位置的保留位或字线的存储垫
公开(公告)号：US5615156A
公开(公告)日：1997-03-25
申请号：US250130
申请日：1994-05-27
申请人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
发明人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80
摘要： A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.
摘要翻译：具有备用位线或字线的半导体存储器件，用于替换有缺陷的位线或字线，这些位线或字线可以增加缺陷消除概率并提高操作余量。保留位线或字线大致设置在存储垫的中央部分。由于在备用字线或位线中存在缺陷发生的可能性低的情况，当用保留字线或位线替换缺陷字线或位线时，可能会使缺陷发生的概率变低。

4. 发明授权

US06274895B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06274895B1
公开(公告)日：2001-08-14
申请号：US09385631
申请日：1999-08-27
申请人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
发明人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
IPC分类号： H01L2710
CPC分类号： H01L27/10897 , G11C5/025 , G11C11/4097 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.
摘要翻译：具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。在每个单位区域上形成沿第一方向延伸的第一互连。沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。在每个单元区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式，根据需要，根据与其相邻的布线专用区域的组合。

5. 发明授权

US06707139B2 Semiconductor device with plural unit regions in which one or more MOSFETs are formed 有权
标题翻译：具有多个单位区域的半导体器件，其中形成有一个或多个MOSFET
公开(公告)号：US06707139B2
公开(公告)日：2004-03-16
申请号：US09928497
申请日：2001-08-14
申请人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
发明人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
IPC分类号： H01L2348
CPC分类号： H01L27/10897 , G11C5/025 , G11C11/4097 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.
摘要翻译：具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。在每个单位区域上形成沿第一方向延伸的第一互连。沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。

6. 发明授权

US06518835B2 Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance 有权
标题翻译：具有最佳电路布局以确保内部源电压的稳定而不降低电路功能和/或操作性能的半导体集成电路器件
公开(公告)号：US06518835B2
公开(公告)日：2003-02-11
申请号：US10142897
申请日：2002-05-13
申请人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
发明人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
IPC分类号： H01L2500
CPC分类号： H01L23/5222 , H01L23/50 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.
摘要翻译：一种半导体集成电路器件，包括：第一互连沟道，包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层;第二互连沟道，包括多个第三层金属互连层，第二方向垂直于第一方向;内部电源电路，其接收从外部端子提供的源极电压并产生与源极电压不同的电压，并且设置有稳定电容器，形成大部分稳定化电容器在第二和第三层金属互连线彼此相交的区域中。

7. 发明授权

US06411160B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06411160B1
公开(公告)日：2002-06-25
申请号：US09376470
申请日：1999-08-18
申请人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
发明人： Yoshiro Riho , Kiyoshi Nakai , Hidekazu Egawa , Yukihide Suzuki , Isamu Fujii
IPC分类号： H01L2500
CPC分类号： H01L23/5222 , H01L23/50 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.
摘要翻译：在一种半导体集成电路器件中，包括第一互连通道，第一互连通道包括在半导体芯片上沿第一方向延伸的多个第二层金属互连层，第二互连通道，包括在第二互连层中延伸的多个第三层金属互连层内部电源电路，其接收从外部端子提供的源极电压，并产生与源极电压不同的电压，并且设置有稳定电容器，大部分稳定化电容器处于第二和第三层金属互连线彼此相交的区域。

8. 发明授权

US08094483B2 Semiconductor device including bit line groups 有权
标题翻译：半导体器件包括位线组
公开(公告)号：US08094483B2
公开(公告)日：2012-01-10
申请号：US12628835
申请日：2009-12-01
申请人： Kiyoshi Nakai , Shuichi Tsukada
发明人： Kiyoshi Nakai , Shuichi Tsukada
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/18 , G11C2207/005
摘要： A semiconductor device includes: a first read/write amplifier; a second read/write amplifier; a first group of bit lines belonging to the first read/write amplifier; a second group of bit lines belonging to the second read/write amplifier and mixed with the first group of bit lines. One of the first group of bit lines and one of the second group of bit lines are selected in parallel. A reference potential is supplied to at least one of the first non-selected bit lines adjacent to the first selected bit line selected from the first group of bit lines, and to at least one of the second non-selected bit lines adjacent to the second selected bit line selected from the first group of bit lines. At least one of remaining ones of the first and second non-selected bit lines is set into a floating state.
摘要翻译：半导体器件包括：第一读/写放大器; 第二读/写放大器; 属于第一读/写放大器的第一组位线; 属于第二读/写放大器的第二组位线，并与第一组位线混合。第一组位线之一和第二组位线之一并行选择。将参考电位提供给与从第一组位线选择的第一选定位线相邻的第一非选择位线中的至少一个以及与第二组相邻的第二非选择位线中的至少一个从第一组位线选择的选定位线。将第一和第二未选择位线中的剩余的位中的至少一个设置为浮置状态。

9. 发明授权

US07554147B2 Memory device and manufacturing method thereof 失效
标题翻译：存储器件及其制造方法
公开(公告)号：US07554147B2
公开(公告)日：2009-06-30
申请号：US11374074
申请日：2006-03-14
申请人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
发明人： Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai , Yukio Fuji , Kazuhiko Kajigaya
IPC分类号： H01L27/108
CPC分类号： G11C13/0004 , G11C11/005 , H01L27/10894 , H01L27/10897 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.
摘要翻译：其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器连接在DRAM位线和PCRAM位线之间。存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。电容元件的下电极和相变存储元件的下电极形成在共用导电层上。

10. 发明授权

US07528402B2 Electrically rewritable non-volatile memory element 有权
标题翻译：电可重写的非易失性存储元件
公开(公告)号：US07528402B2
公开(公告)日：2009-05-05
申请号：US11594879
申请日：2006-11-09
申请人： Homare Sato , Kiyoshi Nakai
发明人： Homare Sato , Kiyoshi Nakai
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording layer pattern and that has a plurality of apertures for exposing one portion of the lower electrode. The lower electrode and the recording layer pattern are connected in each aperture. The apertures extend in the X direction in parallel to one another. The recording layer patterns extend in the Y direction in parallel to one another. Thus the aperture can be formed with higher accuracy as compared to forming an independent aperture. Accordingly, high heating efficiency can be obtained while effectively preventing occurrence of poor connection or the like.
摘要翻译：一种非易失性半导体存储器件包括以矩阵方式布置的多个下电极，多个记录层图案，每个记录层图案布置在下电极上，其中包含相变材料，以及层间绝缘膜，下电极和记录层图案，并且具有用于暴露下电极的一部分的多个孔。下电极和记录层图案连接在每个孔中。孔在X方向上彼此平行地延伸。记录层图案在Y方向上彼此平行地延伸。因此，与形成独立的孔相比，可以以更高的精度形成孔。因此，可以有效地防止连接不良等的发生而获得高的加热效率。

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