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1. 发明授权

US06298435B1 Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor 失效
标题翻译：利用虚拟缓冲区来增加流水线处理器中的指令并行性的方法和装置
公开(公告)号：US06298435B1
公开(公告)日：2001-10-02
申请号：US08633267
申请日：1996-04-16
申请人： Kin Shing Chan , Hung Qui Le , Dung Quoc Nguyen
发明人： Kin Shing Chan , Hung Qui Le , Dung Quoc Nguyen
IPC分类号： G06F930
CPC分类号： G06F9/384 , G06F9/3857
摘要： A method and apparatus for increasing instruction level parallelism using a buffer pointer assignment scheme is implemented whereby rename buffers are assigned during dispatch even though the physical rename registers may not yet be available. These virtual rename buffers are assigned by a buffer pointer assignment table. A virtual bit implemented along with each of the physical rename registers is flipped when an instruction corresponding to the entry stored within a particular physical rename register is completed and the result written to the architected register. Thus, at dispatch time, rename registers are assigned as if there were more rename buffers than there existed physical rename registers.
摘要翻译：实现使用缓冲器指针分配方案来增加指令级并行性的方法和装置，由此在调度期间分配重命名缓冲器，即使物理重命名寄存器可能尚不可用。这些虚拟重命名缓冲区由缓冲区指针分配表分配。当与存储在特定物理重命名寄存器中的条目相对应的指令完成并将结果写入架构寄存器时，与每个物理重命名寄存器一起实现的虚拟位被翻转。因此，在调度时间，重命名寄存器被分配，就好像存在比存在的物理重命名寄存器更多的重命名缓冲区。

2. 发明授权

US5805876A Method and system for reducing average branch resolution time and effective misprediction penalty in a processor 失效
标题翻译：减少处理器中平均分支分辨率时间和有效误判处罚的方法和系统
公开(公告)号：US5805876A
公开(公告)日：1998-09-08
申请号：US723171
申请日：1996-09-30
申请人： Pradip Bose , Kin Shing Chan , Hung Qui Le , Robert Eric Wasmuth
发明人： Pradip Bose , Kin Shing Chan , Hung Qui Le , Robert Eric Wasmuth
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844 , G06F9/3861
摘要： Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of conditional branches located within the first position of the primary instruction buffer within the processor enabling the overall branch processing logic to bypass history table-based prediction logic for such branches without crossing the cycle boundary. Thus, penalties associated with possible mispredictions for this subset of conditional branches are avoided.
摘要翻译：逻辑电路提供了高性能超标量处理器中条件分支指令的快速分辨率。逻辑电路设备处理位于处理器内的主指令缓冲器的第一位置内的条件分支的子集的早（快）分辨率，使得整个分支处理逻辑能够绕过这样的分支的历史表格预测逻辑，而不会跨越周期边界。因此，避免了与该子集条件分支的可能的错误预测相关的惩罚。

3. 发明授权

US06240487B1 Integrated cache buffers 失效
标题翻译：集成缓存缓存
公开(公告)号：US06240487B1
公开(公告)日：2001-05-29
申请号：US09025606
申请日：1998-02-18
申请人： Pei-Chun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Stephen Tung , Dwain Alan Hicks , Kin Shing Chan
发明人： Pei-Chun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Stephen Tung , Dwain Alan Hicks , Kin Shing Chan
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F12/0851
摘要： A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.
摘要翻译：高速缓存具有用于保存数据或指令值的阵列，连接到该阵列的缓冲器，以及用于访问缓冲器以检索处理单元的值的装置。访问装置使用具有基本上等于高速缓存阵列的线间距的间距的线。多路复用器可以与多个这样的缓冲器一起使用以创建公共输出路径。高速缓存可以被交织，阵列是第一子阵列，缓冲器是第一缓冲器，并且还包括第二子阵列和第二缓冲器，其中第一和第二缓冲器分离第一和第二子阵列。本发明可以应用于存储缓冲器以及重新加载缓冲器。

4. 发明授权

US06298417B1 Pipelined cache memory deallocation and storeback 有权
标题翻译：流水线缓存存储器释放和存储
公开(公告)号：US06298417B1
公开(公告)日：2001-10-02
申请号：US09196906
申请日：1998-11-20
申请人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1200
CPC分类号： G06F12/0859 , G06F12/0804
摘要： A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit. This deallocation of the first line of the cache memory occurs regardless of a completion status of the bus interface unit transfer whereby a pending fill of the first cache line may proceed prior to completion of the bus interface unit transfer. In one embodiment, the storeback buffer includes first and second segments for storing first and second segment data respectively. In this embodiment, the deallocation pipelining circuit is able to detect the completion of the transfer of the first segment data during the bus interface unit transfer and preferably configured to initiate an SBB transfer of second line data from a second line in the cache memory array in response to the completion of the first segment data transfer. In this manner, the initiation of the second line SBB transfer precedes the completion of the first line bus interface unit transfer.
摘要翻译：用于高速缓存存储器子系统中的一个释放流水线电路。流水线电路被配置为如果分配流水线电路检测到与第一行对应的高速缓存未命中信号并且将第一行数据标识为第一行数据，则启动存储在高速缓冲存储器阵列的第一行中的第一行数据的存储缓冲器（SBB）传送修改数据。配置流水线电路被配置为在SBB传送完成之后向总线接口单元发出存储请求信号。在从总线接口单元接收到数据确认信号之后，该电路启动总线接口单元传送第一行数据。流水线电路还被配置为在从总线接口单元接收到请求确认信号之后解除对高速缓冲存储器的第一行的分配。无论总线接口单元传送的完成状态如何，高速缓冲存储器的第一行的解除分配都会发生，从而可以在完成总线接口单元传输之前继续执行第一高速缓存行的填充。在一个实施例中，存储缓冲器包括用于分别存储第一和第二段数据的第一和第二段。在该实施例中，解除分配流水线电路能够在总线接口单元传送期间检测到第一段数据的传送完成，并且优选地被配置为发起来自高速缓存存储器阵列中的第二行的第二行数据的SBB传送响应完成第一段数据传输。以这种方式，第二线路SBB传送的启动先于第一线路总线接口单元传送的完成。

5. 发明授权

US5974240A Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution 失效
标题翻译：用于在具有无序和推测性指令执行的数据处理系统中缓冲条件码数据的方法和系统
公开(公告)号：US5974240A
公开(公告)日：1999-10-26
申请号：US480999
申请日：1995-06-07
申请人： Kin Shing Chan
发明人： Kin Shing Chan
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： In response to dispatching a condition register modifying instruction to an execution unit, a condition register rename buffer is associated with such a condition register modifying instruction. The instruction is then executed in the execution unit. Following the execution of the condition register modifying instruction, condition register data is set in the condition register rename buffer to reflect the result of such instruction execution. Additionally, an indicator is set to indicate the condition register data is valid. At the time for completing the condition register modifying instruction, the condition register data is transferred from the condition register rename buffer to the architected condition register, thereby permitting condition register modifying instructions to be dispatched, executed, and finished before the condition register is available to complete each condition register modifying instruction.
摘要翻译：响应于向执行单元调度条件寄存器修改指令，条件寄存器重命名缓冲器与这种条件寄存器修改指令相关联。然后在执行单元中执行该指令。在执行条件寄存器修改指令之后，条件寄存器数据被设置在条件寄存器重命名缓冲器中以反映这种指令执行的结果。此外，指示符被设置以指示条件寄存器数据有效。在完成条件寄存器修改指令时，条件寄存器数据从条件寄存器重命名缓冲器传送到架构条件寄存器，从而允许条件寄存器修改指令在条件寄存器可用之前被调度，执行和完成完成每个条件寄存器修改指令。

6. 发明授权

US5828895A Methods and system for predecoding instructions in a superscalar data processing system 失效
标题翻译：超标量数据处理系统中预解码指令的方法和系统
公开(公告)号：US5828895A
公开(公告)日：1998-10-27
申请号：US531882
申请日：1995-09-20
申请人： Kin Shing Chan , Ravindra Kumar Nair
发明人： Kin Shing Chan , Ravindra Kumar Nair
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30094 , G06F9/30163 , G06F9/30167 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction belongs is selected from multiple instruction categories. Types of data processing system resources required for instruction execution and a quantity of each type of resource required are determined. Thereafter, a plurality of decode bits are calculated, wherein the decode bits represent a particular instruction category in which the instruction belongs and the type and quantity of each data processing system resource required for execution of the instruction. Thereafter, the instruction and the predecode bits are stored in instruction cache. The predecode bits enable the dispatch unit to efficiently, and without fully decoding the instruction at dispatch time, select an execution unit for executing the instruction and determine if the data processing system resources required for execution of the instruction are available before the dispatch unit dispatches the instruction.
摘要翻译：响应于从主存储器重新加载用于存储在超标量数据处理系统中的指令高速缓存中的指令，从多个指令类别中选择指令所属的特定指令类别。确定指令执行所需的数据处理系统资源的类型和所需的每种类型的资源的数量。此后，计算多个解码位，其中解码位表示指令所属的特定指令类别以及执行指令所需的每个数据处理系统资源的类型和数量。此后，指令和预解码位存储在指令高速缓存中。预分解位使得调度单元能够有效地并且在调度时没有完全解码指令的情况下，选择用于执行指令的执行单元，并且在调度单元调度之前确定执行指令所需的数据处理系统资源是否可用指令。

7. 发明申请

US20190077536A1 SPILL RESISTANT DISPOSABLE CUP 审中-公开
公开(公告)号：US20190077536A1
公开(公告)日：2019-03-14
申请号：US16127525
申请日：2018-09-11
申请人： Kin Shing Chan , Eric Ping Pang Chan
发明人： Kin Shing Chan , Eric Ping Pang Chan
IPC分类号： B65D3/20 , B65D3/04 , B65D3/06
摘要： A spill resistant disposable cup is comprised of a sheet of flexible material rolled into a cylindrical or frustoconical shape sealed at its edges and with a sealed bottom. The cup has at least three tabs that can be folded down in an overlapping manner to close the top of the cup. The tabs contain an interlocking mechanism to lock folded tabs in place. Two of the tabs are spaced apart to define a gap and a drinking opening when the tabs are folded down. The tabs can be shaped to form an internal sealing edge that provides resistance from leakage and spills if the cup is tipped when full.

8. 发明授权

US06446170B1 Efficient store machine in cache based microprocessor 失效
标题翻译：高效存储机器在基于缓存的微处理器中
公开(公告)号：US06446170B1
公开(公告)日：2002-09-03
申请号：US09232239
申请日：1999-01-19
申请人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1200
CPC分类号： G06F9/3824
摘要： A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access. The first and second cache accesses preferably occur in consecutive cycles. Typically, the first and second operations are store operations that are queued in the stack in program order. In one embodiment the first operation is removed from the stack upon resolving of the resource conflict.
摘要翻译：一种退出到缓存的操作的方法。最初，第一操作在诸如退出单元的存储队列的堆栈中排队。然后，响应于防止第一操作访问高速缓存的资源冲突，第一操作在第一传送中被复制到被称为未命中锁存器的锁存器。在资源冲突的持续时间内，第一个操作被保留在堆栈中。当解决资源冲突时，在第一个高速缓存访问中，缓存从堆栈中进行第一个操作。优选地，当解决资源冲突并启动第一高速缓存访问时，第一操作从堆栈中移除。在优选实施例中，第一操作保持在未命中锁存器中，直到第一高速缓存访问导致高速缓存命中。本发明的一个实施例还包括响应于由第一高速缓存访问引起的高速缓存未命中，以第一未命中访问的速度访问来自未命中锁存器的第一操作。在当前优选的实施例中，响应于由第一高速缓存访问导致的高速缓存命中，执行第二访问以访问在堆栈中排队的第二操作的高速缓存。第一和第二高速缓存访问优选地在连续的周期中进行。通常，第一和第二操作是以程序顺序排列在堆栈中的存储操作。在一个实施例中，在解决资源冲突时，第一操作从堆栈中移除。

9. 发明授权

US06202128B1 Method and system for pre-fetch cache interrogation using snoop port 失效
标题翻译：使用snoop端口预取缓存询问的方法和系统
公开(公告)号：US06202128B1
公开(公告)日：2001-03-13
申请号：US09038422
申请日：1998-03-11
申请人： Kin Shing Chan , Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1208
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/1054
摘要： An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not. The snoop read access uses a (33-bit) real address to access the data cache without occupying a data port during testing of the pre-fetching stream hits. Therefore, the two Effective Address (EA) accesses and a RCAM snoop access can access the data cache simultaneously thereby increasing pre-fetching performance.
摘要翻译：提供划分为两个子阵列的交错数据高速缓存阵列用于数据处理系统内的利用。每个子阵列包括多条高速缓存线，其中每条高速缓存线包括选定的数据块，奇偶校验字段，包含所选择的数据块的有效地址（ECAM）的一部分的内容可寻址字段，第二内容可寻址字段包含用于所选数据块的实际地址（RCAM）和数据状态字段。分离的有效地址端口（EA）和实际地址端口（RA）允许并行访问高速缓存，而不会在单独的子阵列中发生冲突，并提供子阵列仲裁逻辑电路，用于通过有效地址端口（EA）同时访问单个子阵列）和实际地址端口（RA）。正常字线由有效地址端口或实地址端口通过子阵列仲裁提供和激活。现有的Real Address（RA）缓存侦听端口用于检查预取流的线路访问是否是真正的缓存命中。在测试预取流命中期间，窥探读取访问使用（33位）实地址访问数据高速缓存，而不占用数据端口。因此，两个有效地址（EA）访问和RCAM侦听访问可以同时访问数据高速缓存，从而增加预取性能。

10. 发明授权

US06185674B2 Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor 失效
标题翻译：用于重构在流水线处理器中要完成的下一条指令的地址的方法和装置
公开(公告)号：US06185674B2
公开(公告)日：2001-02-06
申请号：US08417421
申请日：1995-04-05
申请人： Kin Shing Chan , Chiao-Mei Chuang , Alessandro Marchioro
发明人： Kin Shing Chan , Chiao-Mei Chuang , Alessandro Marchioro
IPC分类号： G06F900
CPC分类号： G06F9/322
摘要： A computer processing unit is provided that includes an apparatus for generating an address of the next instruction to be completed. The apparatus includes a first table for storing a plurality of entries each corresponding to a dispatched instruction, each entry comprising an identifier that identifies the corresponding instruction and a status bit that indicates if the corresponding instruction is completed; a second table for storing a plurality of entries each corresponding to dispatched branch instructions, each entry comprising the same identifier stored in the first table, a target address of the dispatched branch instruction and a resolution status field that indicates at least if the corresponding branch instruction has been resolved taken or has been resolved not taken; program counter update logic that, in each machine cycle, updates a program counter to store and output the address of the next instruction to be completed according to the entries stored in the first table and the second table. Because the first and second tables employ efficient identification tags to identify instructions that modify the control flow of the execution pipeline and the target address of such instructions, the computer processing unit of the present invention need not store the full address of each instruction in the execution pipeline to update the program counter as is conventional, and thus saves real estate that may be used for other circuitry.
摘要翻译：提供一种计算机处理单元，其包括用于生成要完成的下一条指令的地址的装置。该装置包括：第一表，用于存储与分派指令对应的多个条目;每个条目包括识别对应指令的标识符和指示相应指令是否完成的状态位; 用于存储多个条目的第二表，每个条目各自对应于分派的分支指令，每个条目包括存储在第一表中的相同标识符，分派的分支指令的目标地址和分辨率状态字段，其至少指示相应的分支指令已解决或已解决不采取; 程序计数器更新逻辑，其在每个机器周期中根据存储在第一表和第二表中的条目更新程序计数器以存储和输出要完成的下一个指令的地址。因为第一和第二表使用有效用于识别修改执行流水线的控制流程和这些指令的目标地址的指令的识别标签，本发明的计算机处理单元不需要在执行流水线中存储每条指令的完整地址以更新程序计数器并且因此节省可用于其它电路的不动产。

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