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1. 发明授权

US06202128B1 Method and system for pre-fetch cache interrogation using snoop port 失效
标题翻译：使用snoop端口预取缓存询问的方法和系统
公开(公告)号：US06202128B1
公开(公告)日：2001-03-13
申请号：US09038422
申请日：1998-03-11
申请人： Kin Shing Chan , Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1208
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/1054
摘要： An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not. The snoop read access uses a (33-bit) real address to access the data cache without occupying a data port during testing of the pre-fetching stream hits. Therefore, the two Effective Address (EA) accesses and a RCAM snoop access can access the data cache simultaneously thereby increasing pre-fetching performance.
摘要翻译：提供划分为两个子阵列的交错数据高速缓存阵列用于数据处理系统内的利用。每个子阵列包括多条高速缓存线，其中每条高速缓存线包括选定的数据块，奇偶校验字段，包含所选择的数据块的有效地址（ECAM）的一部分的内容可寻址字段，第二内容可寻址字段包含用于所选数据块的实际地址（RCAM）和数据状态字段。分离的有效地址端口（EA）和实际地址端口（RA）允许并行访问高速缓存，而不会在单独的子阵列中发生冲突，并提供子阵列仲裁逻辑电路，用于通过有效地址端口（EA）同时访问单个子阵列）和实际地址端口（RA）。正常字线由有效地址端口或实地址端口通过子阵列仲裁提供和激活。现有的Real Address（RA）缓存侦听端口用于检查预取流的线路访问是否是真正的缓存命中。在测试预取流命中期间，窥探读取访问使用（33位）实地址访问数据高速缓存，而不占用数据端口。因此，两个有效地址（EA）访问和RCAM侦听访问可以同时访问数据高速缓存，从而增加预取性能。

2. 发明授权

US06298417B1 Pipelined cache memory deallocation and storeback 有权
标题翻译：流水线缓存存储器释放和存储
公开(公告)号：US06298417B1
公开(公告)日：2001-10-02
申请号：US09196906
申请日：1998-11-20
申请人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1200
CPC分类号： G06F12/0859 , G06F12/0804
摘要： A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit. This deallocation of the first line of the cache memory occurs regardless of a completion status of the bus interface unit transfer whereby a pending fill of the first cache line may proceed prior to completion of the bus interface unit transfer. In one embodiment, the storeback buffer includes first and second segments for storing first and second segment data respectively. In this embodiment, the deallocation pipelining circuit is able to detect the completion of the transfer of the first segment data during the bus interface unit transfer and preferably configured to initiate an SBB transfer of second line data from a second line in the cache memory array in response to the completion of the first segment data transfer. In this manner, the initiation of the second line SBB transfer precedes the completion of the first line bus interface unit transfer.
摘要翻译：用于高速缓存存储器子系统中的一个释放流水线电路。流水线电路被配置为如果分配流水线电路检测到与第一行对应的高速缓存未命中信号并且将第一行数据标识为第一行数据，则启动存储在高速缓冲存储器阵列的第一行中的第一行数据的存储缓冲器（SBB）传送修改数据。配置流水线电路被配置为在SBB传送完成之后向总线接口单元发出存储请求信号。在从总线接口单元接收到数据确认信号之后，该电路启动总线接口单元传送第一行数据。流水线电路还被配置为在从总线接口单元接收到请求确认信号之后解除对高速缓冲存储器的第一行的分配。无论总线接口单元传送的完成状态如何，高速缓冲存储器的第一行的解除分配都会发生，从而可以在完成总线接口单元传输之前继续执行第一高速缓存行的填充。在一个实施例中，存储缓冲器包括用于分别存储第一和第二段数据的第一和第二段。在该实施例中，解除分配流水线电路能够在总线接口单元传送期间检测到第一段数据的传送完成，并且优选地被配置为发起来自高速缓存存储器阵列中的第二行的第二行数据的SBB传送响应完成第一段数据传输。以这种方式，第二线路SBB传送的启动先于第一线路总线接口单元传送的完成。

3. 发明授权

US06446170B1 Efficient store machine in cache based microprocessor 失效
标题翻译：高效存储机器在基于缓存的微处理器中
公开(公告)号：US06446170B1
公开(公告)日：2002-09-03
申请号：US09232239
申请日：1999-01-19
申请人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
发明人： Kin Shing Chan , Dwain Alan Hicks , Michael John Mayfield , Shih-Hsiung Stephen Tung
IPC分类号： G06F1200
CPC分类号： G06F9/3824
摘要： A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access. The first and second cache accesses preferably occur in consecutive cycles. Typically, the first and second operations are store operations that are queued in the stack in program order. In one embodiment the first operation is removed from the stack upon resolving of the resource conflict.
摘要翻译：一种退出到缓存的操作的方法。最初，第一操作在诸如退出单元的存储队列的堆栈中排队。然后，响应于防止第一操作访问高速缓存的资源冲突，第一操作在第一传送中被复制到被称为未命中锁存器的锁存器。在资源冲突的持续时间内，第一个操作被保留在堆栈中。当解决资源冲突时，在第一个高速缓存访问中，缓存从堆栈中进行第一个操作。优选地，当解决资源冲突并启动第一高速缓存访问时，第一操作从堆栈中移除。在优选实施例中，第一操作保持在未命中锁存器中，直到第一高速缓存访问导致高速缓存命中。本发明的一个实施例还包括响应于由第一高速缓存访问引起的高速缓存未命中，以第一未命中访问的速度访问来自未命中锁存器的第一操作。在当前优选的实施例中，响应于由第一高速缓存访问导致的高速缓存命中，执行第二访问以访问在堆栈中排队的第二操作的高速缓存。第一和第二高速缓存访问优选地在连续的周期中进行。通常，第一和第二操作是以程序顺序排列在堆栈中的存储操作。在一个实施例中，在解决资源冲突时，第一操作从堆栈中移除。

4. 发明授权

US06240487B1 Integrated cache buffers 失效
标题翻译：集成缓存缓存
公开(公告)号：US06240487B1
公开(公告)日：2001-05-29
申请号：US09025606
申请日：1998-02-18
申请人： Pei-Chun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Stephen Tung , Dwain Alan Hicks , Kin Shing Chan
发明人： Pei-Chun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Stephen Tung , Dwain Alan Hicks , Kin Shing Chan
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F12/0851
摘要： A cache has an array for holding data or instruction values, a buffer connected to the array, and means for accessing the buffer to retrieve a value for a processing unit. The accessing means uses wires having a pitch which is substantially equal to a wire pitch of the cache array. Multiplexers can be used with a plurality of such buffers to create a common output path. The cache can be interleaved, with the array being a first subarray, and the buffer being a first buffer, and further comprising a second subarray and a second buffer, wherein the first and second buffers separate the first and second subarrays. The invention can be applied to a store-back buffer as well as a reload buffer.
摘要翻译：高速缓存具有用于保存数据或指令值的阵列，连接到该阵列的缓冲器，以及用于访问缓冲器以检索处理单元的值的装置。访问装置使用具有基本上等于高速缓存阵列的线间距的间距的线。多路复用器可以与多个这样的缓冲器一起使用以创建公共输出路径。高速缓存可以被交织，阵列是第一子阵列，缓冲器是第一缓冲器，并且还包括第二子阵列和第二缓冲器，其中第一和第二缓冲器分离第一和第二子阵列。本发明可以应用于存储缓冲器以及重新加载缓冲器。

5. 发明授权

US6085291A System and method for selectively controlling fetching and prefetching of data to a processor 失效
标题翻译：用于选择性地控制将数据提取和预取到处理器的系统和方法
公开(公告)号：US6085291A
公开(公告)日：2000-07-04
申请号：US554180
申请日：1995-11-06
申请人： Dwain Alan Hicks , Michael John Mayfield , David Scott Ray , Shih-Hsiung Stephen Tung
发明人： Dwain Alan Hicks , Michael John Mayfield , David Scott Ray , Shih-Hsiung Stephen Tung
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/383 , G06F12/0862 , G06F2212/6022 , G06F2212/6026
摘要： Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.
摘要翻译：在实现主和次高速缓存和流过滤器和缓冲器的数据处理系统中，缓存行的预取以渐进的方式执行。在一种模式下，数据可能不被预取。在第二模式中，预取两条高速缓存线，其中一行被预取到L1高速缓存中，并且下一行被预取到流缓冲器中。在第三种模式下，一次预取多于两条的高速缓存行。可以在高速缓存未命中或命中时执行预取。连续缓存行上的缓存未命中可能会将流缓存行分配给流缓冲区。耦合到流滤波器电路的控制电路选择性地控制数据从系统存储器到与处理器和流缓冲器电路相关联的主和次高速缓存的取样和预取。

6. 发明授权

US5787478A Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy 失效
标题翻译：用于实现高速缓存一致机制以用于非包容性高速缓存存储器层次结构内的利用的方法和系统
公开(公告)号：US5787478A
公开(公告)日：1998-07-28
申请号：US810775
申请日：1997-03-05
申请人： Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Rajinder Paul Singh
发明人： Dwain Alan Hicks , Peichun Peter Liu , Michael John Mayfield , Rajinder Paul Singh
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811
摘要： A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.
摘要翻译：公开了一种实现用于在数据处理系统内支持非包容性高速缓存存储器层级的高速缓存一致性机制的方法和系统。根据本发明的方法和系统，存储器层级包括主高速缓冲存储器，副高速缓冲存储器和主存储器。主缓冲存储器和次高速缓冲存储器是不包含的。此外，与主缓存器的每个高速缓存行相关联地，在主缓存器内提供第一状态位和第二状态位。作为优选实施例，仅当在一级高速缓冲存储器中的对应的高速缓存行已经在直写模式下被修改时才设置第一状态位，而仅当相应的高速缓存行也存在于次级高速缓存存储器。这样，可以通过利用主高速缓存存储器中的第一状态位和第二状态位来维持主高速缓存存储器和辅助高速缓冲存储器之间的高速缓存一致性。

7. 发明授权

US07464242B2 Method of load/store dependencies detection with dynamically changing address length 失效
标题翻译：使用动态变化的地址长度进行加载/存储依赖关系检测的方法
公开(公告)号：US07464242B2
公开(公告)日：2008-12-09
申请号：US11050039
申请日：2005-02-03
申请人： Brian David Barrick , Dwain Alan Hicks , Takeki Osanai , David Scott Ray
发明人： Brian David Barrick , Dwain Alan Hicks , Takeki Osanai , David Scott Ray
IPC分类号： G06F12/00
CPC分类号： G06F12/0623 , G06F9/383 , G06F9/3834 , G06F9/3861 , G06F12/0802
摘要： A method, an apparatus, and a computer program product are provided for detecting load/store dependency in a memory system by dynamically changing the address width for comparison. An incoming load/store operation must be compared to the operations in the pipeline and the queues to avoid address conflicts. Overall, the present invention introduces a cache hit or cache miss input into the load/store dependency logic. If the incoming load operation is a cache hit, then the quadword boundary address value is used for detection. If the incoming load operation is a cache miss, then the cacheline boundary address value is used for detection. This invention enhances the performance of LHS and LHR operations in a memory system.
摘要翻译：提供了一种方法，装置和计算机程序产品，用于通过动态地改变地址宽度进行比较来检测存储器系统中的加载/存储相关性。必须将进入的加载/存储操作与流水线和队列中的操作进行比较，以避免地址冲突。总的来说，本发明将缓存命中或高速缓存未命中输入引入到加载/存储依赖逻辑中。如果进入加载操作是缓存命中，则使用四字边界地址值进行检测。如果进入加载操作是高速缓存未命中，则使用高速缓存行边界地址值进行检测。本发明增强了存储系统中LHS和LHR操作的性能。

8. 发明申请

US20080141014A1 LOAD ADDRESS DEPENDENCY MECHANISM SYSTEM AND METHOD IN A HIGH FREQUENCY, LOW POWER PROCESSOR SYSTEM 失效
标题翻译：低频处理器系统中的负载地址依赖机制和方法
公开(公告)号：US20080141014A1
公开(公告)日：2008-06-12
申请号：US12025658
申请日：2008-02-04
申请人： Brian David Barrick , Kimberly Marie Fensler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
发明人： Brian David Barrick , Kimberly Marie Fensler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/3838
摘要： The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
摘要翻译：本发明提供了一种用于高频，低功率处理器中的负载地址依赖机制的方法。接收对应于存储器地址的加载指令。识别与存储器地址相对应的至少一个未执行的先前指令。加载指令存储在缺省队列中。并且加载指令被标记为本地缺失。

9. 发明授权

US5953351A Method and apparatus for indicating uncorrectable data errors 失效
标题翻译：用于指示不可校正数据错误的方法和装置
公开(公告)号：US5953351A
公开(公告)日：1999-09-14
申请号：US529125
申请日：1995-09-15
申请人： Dwain Alan Hicks , Avery Cox Topps
发明人： Dwain Alan Hicks , Avery Cox Topps
IPC分类号： G06F11/10 , G11C29/00
CPC分类号： G06F11/1024
摘要： A method and apparatus for identifying data that contains an uncorrectable error may be accomplished in a computer that includes a memory unit operably coupled to a processor. The memory unit includes an error detection circuit that, when an uncorrectable storage error is detected, produces transmit check bits indicating that the data being transmitted includes an uncorrectable storage error. The processor, which includes a check bit decoder, upon receiving the transmit check bits, interprets the transmit check bits to identify the uncorrectable error. When the uncorrectable error is identified, the check bit decoder provides a data error signal to a processing core of the processor, thereby interrupting the processing core which avoids a system error and the need to reboot the computer.
摘要翻译：用于识别包含不可校正错误的数据的方法和装置可以在包括可操作地耦合到处理器的存储器单元的计算机中完成。存储器单元包括错误检测电路，当检测到不可校正的存储错误时，产生指示被发送的数据包括不可校正的存储错误的发送校验位。包括校验位解码器的处理器在接收到发送校验位时解释发送校验位以识别不可校正误差。当识别出不可校正的错误时，校验位解码器向处理器的处理核心提供数据错误信号，从而中断处理核心，避免了系统错误和需要重启计算机。

10. 发明授权

US07769985B2 Load address dependency mechanism system and method in a high frequency, low power processor system 失效
标题翻译：在高频，低功耗处理器系统中加载地址依赖机制系统和方法
公开(公告)号：US07769985B2
公开(公告)日：2010-08-03
申请号：US12025658
申请日：2008-02-04
申请人： Brian David Barrick , Kimberly Marie Fernsler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
发明人： Brian David Barrick , Kimberly Marie Fernsler , Dwain Alan Hicks , David Scott Ray , David Shippy , Takeki Osanai
IPC分类号： G06F9/316
CPC分类号： G06F9/3834 , G06F9/3838
摘要： The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.
摘要翻译：本发明提供了一种用于高频，低功率处理器中的负载地址依赖机制的方法。接收对应于存储器地址的加载指令。识别与存储器地址相对应的至少一个未执行的先前指令。加载指令存储在未命中队列中。并且加载指令被标记为本地缺失。

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