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    • 2. 发明授权
    • Secure replay protected storage
    • 安全重放保护存储
    • US09405707B2
    • 2016-08-02
    • US13997896
    • 2011-12-20
    • Nitin V. SarangdharWilliam A. Stevens, Jr.John J. Vranich
    • Nitin V. SarangdharWilliam A. Stevens, Jr.John J. Vranich
    • G06F11/30G06F12/14G06F13/14
    • G06F12/1408G06F13/14G06F21/44G06F21/79G06F2212/1052
    • Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such that it may be protected against user attacks—e.g., replacing the SPI flash memory device or a man-in-the-middle (MITM) attack to modify the SPI flash memory contents on the fly. In the prior art, monotonic counters cannot be stored in SPI flash memory devices because said devices do not provide replay protection for the counters. A user may also remove the flash memory device and reprogram it. Host platforms alone cannot protect against such hardware attacks.Embodiments of the invention enable secure standard storage flash memory devices such as SPI flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and HMAC key logic to create secure execution environments for various components.
    • 本发明的实施例在闪存设备(例如,串行外围设备接口(SPI)闪存设备)中创建底层基础设施,使得其可以被保护免受用户攻击 - 例如,替换SPI闪存设备或管理员 - 中间(MITM)攻击,即时修改SPI闪存内容。 在现有技术中,单调计数器不能存储在SPI闪存设备中,因为所述设备不为计数器提供重放保护。 用户还可以移除闪存设备并对其进行重新编程。 仅主机平台无法防范此类硬件攻击。 本发明的实施例使得诸如SPI闪存设备之类的安全标准存储闪存设备能够实现用于安全存储的数据的重放保护。 本发明的实施例利用闪存控制器,闪存设备,唯一设备密钥和HMAC密钥逻辑来为各种组件创建安全的执行环境。
    • 4. 发明授权
    • Method for SMI arbitration timeliness in a cooperative SMI/driver use mechanism
    • 合作SMI /驾驶员使用机制中SMI仲裁及时性的方法
    • US06981081B2
    • 2005-12-27
    • US10325776
    • 2002-12-19
    • William A. Stevens, Jr.Alberto J. MartinezChristopher J. Spiegel
    • William A. Stevens, Jr.Alberto J. MartinezChristopher J. Spiegel
    • G06F13/14G06F13/24G06F13/378
    • G06F13/378
    • A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a hardware-based semaphore (status bit) to allow either the SMI or the driver to claim ownership of the Bus host controller for an arbitrary period of time. While either the SMI or the driver may own the status bit, the other party must poll the bit until ownership is achieved. For the SMI, this involves scheduling a periodic SMI interrupt. The driver performs self arbitration of claiming the status bit to provide the periodic SMI interrupt the opportunity to claim the bit. The mechanism allows the SMI access to the Bus host controller in a “timely” manner, while minimizing impact to driver access to the Bus host controller, which could impact driver Bus transaction throughput.
    • 总线驱动器实现仲裁机制,允许系统管理中断(SMI)和总线驱动程序协同使用总线主机控制器硬件。 该机制采用基于硬件的信号量(状态位)来允许SMI或驱动程序在任意一段时间内声明对总线主机控制器的所有权。 虽然SMI或驱动程序可能拥有状态位,但是对方必须轮询该位,直到实现所有权。 对于SMI,这涉及调度周期性SMI中断。 驱动程序执行声称状态位的自我仲裁,以使周期性SMI中断有机会声明该位。 该机制允许SMI以“及时”的方式访问总线主机控制器,同时最小化对驱动程序访问总线主机控制器的影响,这可能会影响驱动器总线事务吞吐量。
    • 6. 发明授权
    • Method and apparatus for initializing a computer system that includes disabling the masking of a maskable address line
    • 用于初始化计算机系统的方法和装置,包括禁用掩蔽可屏蔽地址线
    • US06473853B1
    • 2002-10-29
    • US09337369
    • 1999-06-21
    • Christopher J. SpiegelWilliam A. Stevens, Jr.
    • Christopher J. SpiegelWilliam A. Stevens, Jr.
    • G06F9445
    • G06F9/4403
    • A method of securing a boot process for a computer system enables a processor to boot from a location identified by a boot vector. The method includes the step of disabling masking of a maskable address line in response to a processor initialization event. In one embodiment, an apparatus includes a processor coupled to a memory by at least one maskable address line wherein the memory is storing a first initialization instruction. The apparatus includes a mask control wherein the mask control disables masking of the maskable address line before the processor attempts to access the first initialization instruction in response to an initialization event. In one embodiment a processor chipset gates a first address mask control with an inhibit bit to generate a second address mask control. The second address mask control is independent of the first address mask control when the inhibit bit is set to a first value. The processor chipset sets the inhibit bit to the first value in response to a processor initialization event. In various embodiments the initialization event include at least one of an application of power to the processor, a processor RESET, or a processor INIT.
    • 确保计算机系统的引导过程的方法使得处理器能够从由引导向量识别的位置引导。 该方法包括响应于处理器初始化事件禁用可屏蔽地址线的屏蔽的步骤。 在一个实施例中,一种装置包括通过至少一个可屏蔽地址线耦合到存储器的处理器,其中存储器正在存储第一初始化指令。 该设备包括掩模控制,其中掩码控制在处理器响应于初始化事件尝试访问第一初始化指令之前禁用可屏蔽地址线的掩蔽。 在一个实施例中,处理器芯片组用禁止位对第一地址掩码控制进行门控以产生第二地址掩码控制。 当禁止位被设置为第一值时,第二地址掩码控制与第一地址掩码控制无关。 处理器芯片组响应于处理器初始化事件将禁止位设置为第一值。 在各种实施例中,初始化事件包括向处理器施加电力,处理器RESET或处理器INIT中的至少一个。