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    • 4. 发明授权
    • Method for SMI arbitration timeliness in a cooperative SMI/driver use mechanism
    • 合作SMI /驾驶员使用机制中SMI仲裁及时性的方法
    • US06981081B2
    • 2005-12-27
    • US10325776
    • 2002-12-19
    • William A. Stevens, Jr.Alberto J. MartinezChristopher J. Spiegel
    • William A. Stevens, Jr.Alberto J. MartinezChristopher J. Spiegel
    • G06F13/14G06F13/24G06F13/378
    • G06F13/378
    • A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a hardware-based semaphore (status bit) to allow either the SMI or the driver to claim ownership of the Bus host controller for an arbitrary period of time. While either the SMI or the driver may own the status bit, the other party must poll the bit until ownership is achieved. For the SMI, this involves scheduling a periodic SMI interrupt. The driver performs self arbitration of claiming the status bit to provide the periodic SMI interrupt the opportunity to claim the bit. The mechanism allows the SMI access to the Bus host controller in a “timely” manner, while minimizing impact to driver access to the Bus host controller, which could impact driver Bus transaction throughput.
    • 总线驱动器实现仲裁机制,允许系统管理中断(SMI)和总线驱动程序协同使用总线主机控制器硬件。 该机制采用基于硬件的信号量(状态位)来允许SMI或驱动程序在任意一段时间内声明对总线主机控制器的所有权。 虽然SMI或驱动程序可能拥有状态位,但是对方必须轮询该位,直到实现所有权。 对于SMI,这涉及调度周期性SMI中断。 驱动程序执行声称状态位的自我仲裁,以使周期性SMI中断有机会声明该位。 该机制允许SMI以“及时”的方式访问总线主机控制器,同时最小化对驱动程序访问总线主机控制器的影响,这可能会影响驱动器总线事务吞吐量。
    • 6. 发明授权
    • Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec
    • 用于计算机系统的唤醒电路,使得编解码器控制器能够响应于由编解码器检测到唤醒事件而产生系统中断
    • US06564330B1
    • 2003-05-13
    • US09472096
    • 1999-12-23
    • Alberto J. MartinezDavid I. PoisnerKarthi R. Vadivelu
    • Alberto J. MartinezDavid I. PoisnerKarthi R. Vadivelu
    • G06F126
    • G06F1/24
    • A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.
    • 用于具有编解码器控制器的计算机系统的唤醒电路。 当编解码器检测到需要系统激活的事件时,该电路向计算机系统提供唤醒信号。 提供该信号是否编解码器与其控制器之间的通信链路是活动的还是非活动的。 当链路处于非活动状态时,如没有位时钟所示,任何编解码器输入线上的数据信号触发控制器向系统发送电源激活信号并启动编解码器链路的激活。 如果链路已经处于活动状态,则通用输入状态改变位被发送到控制器,控制器将其写入用于触发系统功率激活信号的寄存器。 启用输入允许在程序控制下启用或禁用唤醒信号。 唤醒信号可用于触发适用于启动系统恢复功能的系统管理中断或其他中断。
    • 9. 发明授权
    • Real-time processing of a synchronous or isochronous data stream in the presence of gaps in the data stream due to queue underflow or overflow
    • 在存在由于队列下溢或溢出引起的数据流中的间隙的同步或等时数据流的实时处理
    • US06631429B2
    • 2003-10-07
    • US09471942
    • 1999-12-23
    • Erik C. Cota-RoblesBarry O'MahonyAlberto J. Martinez
    • Erik C. Cota-RoblesBarry O'MahonyAlberto J. Martinez
    • G06F1300
    • H04L12/64H04L25/05
    • In one embodiment of the present invention, an output device sends a spurious data sample in place of a first data sample to be sent from a queue if the queue is in a state of underflow during which the first data sample is not available to be sent. The buffer is to store data samples for an isochronous data transmission. Circuitry skips the first data sample when the first data sample becomes available in the queue so that synchronization for subsequent data samples sent from the queue is preserved. In another embodiment of the present invention, an input device advances an input buffer pointer to point to a next location in a memory in response to receiving a data sample at a queue during a state of overflow. The input buffer pointer indicates a location in the memory to which a next data sample is to be sent from the queue. The queue stores data samples for an isochronous data transmission. By advancing the input buffer pointer, synchronization for subsequent data samples is preserved.
    • 在本发明的一个实施例中,如果队列处于下溢状态,则第一数据样本不可用于发送,则输出设备发送伪数据样本代替要从队列发送的第一数据样本 。 缓冲区用于存储用于同步数据传输的数据样本。 当第一个数据样本在队列中可用时,电路会跳过第一个数据样本,以便保留从队列发送的后续数据样本的同步。 在本发明的另一实施例中,响应于在溢出状态期间在队列处接收到数据样本,输入装置使输入缓冲器指针前进到指向存储器中的下一个位置。 输入缓冲区指针指示要从队列发送下一个数据样本的存储器中的位置。 队列存储用于等时数据传输的数据样本。 通过前进输入缓冲区指针,保留后续数据样本的同步。