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1. 发明授权

US06680500B1 Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers 有权
标题翻译：具有磁性材料层的半导体器件的绝缘覆盖层和导电覆盖层
公开(公告)号：US06680500B1
公开(公告)日：2004-01-20
申请号：US10210742
申请日：2002-07-31
申请人： Kia-Seng Low , John P. Hummel , Igor Kasko , Gregory Costrini
发明人： Kia-Seng Low , John P. Hummel , Igor Kasko , Gregory Costrini
IPC分类号： H01L2982
CPC分类号： H01L27/222 , H01L21/76834 , H01L21/7684 , H01L43/08 , H01L43/12
摘要： A semiconductor device (100) and method of fabrication thereof, wherein a plurality of first conductive lines (116) are formed in a dielectric layer (112) over a substrate (110), and an insulating cap layer (140) is disposed over the first conductive lines (116) and exposed portions of the dielectric layer (112). The insulating cap layer (140) is patterned and etched to expose stack portions of the first conductive lines (116). A conductive cap layer (144) is deposited over the exposed portions of the first conductive lines (116). A magnetic material stack (118) is disposed over the insulating cap layer (140), and the magnetic material stack is etched to form magnetic stacks. The insulating cap layer (140) and conductive cap layer (144) protect the underlying first conductive line (116) material during the etching processes.
摘要翻译：一种半导体器件（100）及其制造方法，其中在衬底（110）上的电介质层（112）中形成多个第一导电线（116），并且绝缘覆盖层（140）设置在第一导电线（116）和介电层（112）的暴露部分。对绝缘覆盖层（140）进行图案化和蚀刻以暴露第一导电线（116）的堆叠部分。导电盖层（144）沉积在第一导线（116）的暴露部分上。磁性材料堆叠（118）设置在绝缘盖层（140）上，并且磁性材料堆叠被蚀刻以形成磁性堆叠。在蚀刻过程期间，绝缘覆盖层（140）和导电覆盖层（144）保护下面的第一导电线（116）材料。

2. 发明授权

US06985384B2 Spacer integration scheme in MRAM technology 有权
标题翻译： MRAM技术中的间隔整合方案
公开(公告)号：US06985384B2
公开(公告)日：2006-01-10
申请号：US10261709
申请日：2002-10-01
申请人： Gregory Costrini , John Hummel , Kia-Seng Low , Igor Kasko , Frank Findeis , Wolfgang Raberg
发明人： Gregory Costrini , John Hummel , Kia-Seng Low , Igor Kasko , Frank Findeis , Wolfgang Raberg
IPC分类号： G11C11/18
CPC分类号： H01L43/12
摘要： A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
摘要翻译：通过蚀刻由缓冲层，钉扎磁性层，隧道势垒层和自由磁性层组成的覆盖金属堆叠来制造磁阻存储器件。通过形成覆盖自由层和隧道屏障界面侧面的保护性间隔物，消除了在蚀刻过程期间与溅射金属接合短路的问题。在通过在阻挡层上停止的自由层的第一次蚀刻之后形成间隔物。在间隔物形成之后，进行第二次蚀刻以隔离该装置。器件隧道结的图案化使用一次性心轴方法制造，其能够在器件图案化工艺完成之后进行自对准接触。

3. 发明授权

US07097777B2 Magnetic switching device 失效
标题翻译：磁性开关装置
公开(公告)号：US07097777B2
公开(公告)日：2006-08-29
申请号：US11070856
申请日：2005-03-02
申请人： Gregory Costrini , John P. Hummel , George Stojakovic , Kia-Seng Low
发明人： Gregory Costrini , John P. Hummel , George Stojakovic , Kia-Seng Low
IPC分类号： B44C1/22
CPC分类号： G11C11/16 , B82Y25/00 , B82Y40/00 , H01F41/308 , H01L43/12
摘要： A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.
摘要翻译：提供一种形成磁性开关装置的方法。该方法包括沉积双层硬掩模，其可以包括氮化钛的第一掩模层和形成在其上的钨的第二掩模层。执行第一光刻处理以对第二掩模层进行图案化，并且执行第二光刻处理以对第一掩模层进行图案化。此后，根据第一掩模层可以对磁性隧道结堆叠进行构图。可以执行蚀刻工艺以根据第二掩模层进一步图案化第一掩模层。可以在第一掩模层和第二掩模层上形成可选的钝化层。

4. 发明授权

US06974770B2 Self-aligned mask to reduce cell layout area 失效
标题翻译：自对准面罩减少细胞布局面积
公开(公告)号：US06974770B2
公开(公告)日：2005-12-13
申请号：US10600034
申请日：2003-06-20
申请人： Gregory Costrini , Kia-Seng Low , David L. Rath , Michael C. Gaidis , Walter Glashauser
发明人： Gregory Costrini , Kia-Seng Low , David L. Rath , Michael C. Gaidis , Walter Glashauser
IPC分类号： H01L21/60 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76897 , H01L21/76834
摘要： Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.
摘要翻译：在相邻的金属化线之间蚀刻的自对准通孔和沟槽允许分配给通孔或沟槽的电介质衬底的面积显着减小，而不增加对相邻金属化线的电短路的可能性。

5. 发明授权

US06743642B2 Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology 失效
标题翻译：双层CMP工艺，提高MRAM技术中磁性堆叠的表面粗糙度
公开(公告)号：US06743642B2
公开(公告)日：2004-06-01
申请号：US10289488
申请日：2002-11-06
申请人： Gregory Costrini , John Hummel , Kia-Seng Low , Mahadevaiyer Krishnan
发明人： Gregory Costrini , John Hummel , Kia-Seng Low , Mahadevaiyer Krishnan
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/26 , H01F10/3254 , H01F41/307 , H01L27/222
摘要： A method for manufacturing a magnetoresistive random access memory (MRAM) cell is disclosed, which alleviates the problem of Neel coupling caused by roughness in the interface between the tunnel junction layer and the magnetic layers. The method includes depositing first and second barrier layers on the conductor, wherein the first barrier layer has a polish rate different from that of the second barrier layer. The second barrier layer is then essentially removed by chemical mechanical polishing (CMP), leaving a very smooth and uniform first barrier layer. When the magnetic stack is then formed on the polished first barrier layer, interfacial roughness is not translated to the tunnel junction layer, and no corruption of magnetization is experienced.
摘要翻译：公开了一种用于制造磁阻随机存取存储器（MRAM）单元的方法，其减轻了由隧道结层和磁性层之间的界面中的粗糙度引起的Neel耦合的问题。该方法包括在导体上沉积第一和第二阻挡层，其中第一阻挡层具有与第二阻挡层不同的抛光速率。然后通过化学机械抛光（CMP）基本上除去第二阻挡层，留下非常平滑和均匀的第一阻挡层。当磁性堆叠形成在抛光的第一阻挡层上时，界面粗糙度不会转变为隧道结层，并且不会发生磁化腐蚀。

6. 发明申请

US20050207064A1 Magnetic switching device 失效
标题翻译：磁性开关装置
公开(公告)号：US20050207064A1
公开(公告)日：2005-09-22
申请号：US11070856
申请日：2005-03-02
申请人： Gregory Costrini , John Hummel , George Stojakovic , Kia-Seng Low
发明人： Gregory Costrini , John Hummel , George Stojakovic , Kia-Seng Low
IPC分类号： G11C11/16 , H01F41/30 , H01L43/12 , G11B21/20
CPC分类号： G11C11/16 , B82Y25/00 , B82Y40/00 , H01F41/308 , H01L43/12
摘要： A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.
摘要翻译：提供一种形成磁性开关装置的方法。该方法包括沉积双层硬掩模，其可以包括氮化钛的第一掩模层和形成在其上的钨的第二掩模层。执行第一光刻处理以对第二掩模层进行图案化，并且执行第二光刻处理以对第一掩模层进行图案化。此后，根据第一掩模层可以对磁性隧道结堆叠进行构图。可以执行蚀刻工艺以根据第二掩模层进一步图案化第一掩模层。可以在第一掩模层和第二掩模层上形成可选的钝化层。

7. 发明申请

US20090189242A1 METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效
标题翻译：用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件
公开(公告)号：US20090189242A1
公开(公告)日：2009-07-30
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译：公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向和具有第二结晶取向的体区。使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

8. 发明申请

US20050277207A1 MASK SCHEMES FOR PATTERNING MAGNETIC TUNNEL JUNCTIONS 失效
标题翻译：用于绘制磁性隧道结的掩蔽方案
公开(公告)号：US20050277207A1
公开(公告)日：2005-12-15
申请号：US10868328
申请日：2004-06-15
申请人： Gregory Costrini , Frank Findeis , Gill Lee , Chanro Park
发明人： Gregory Costrini , Frank Findeis , Gill Lee , Chanro Park
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/22 , H01L43/12
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
摘要翻译：磁记录装置的磁隧道结（MTJ）的图案化方法，可避免在刻蚀过程中将磁存储单元短路到上层的导线。一种方法包括使用具有两个材料层的硬掩模来图案化MTJ的下部磁性材料层。硬掩模的第一种材料是薄的并且包括耐蚀刻材料。沉积在第一材料上的硬掩模的第二材料比第一材料更厚并且耐蚀刻性更差。在下磁性材料层的蚀刻过程期间，至少部分第二材料被牺牲地去除。可以使用保形或非保形材料作为硬掩模的第二材料。用于图形MTJ的较低磁性材料的硬掩模可以包括单层非保形材料。

9. 发明申请

US20110092056A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20110092056A1
公开(公告)日：2011-04-21
申请号：US12977134
申请日：2010-12-23
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/762 , H01L21/3205
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

10. 发明申请

US20070249133A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 审中-公开
标题翻译：用于半导体器件的导电间隔物
公开(公告)号：US20070249133A1
公开(公告)日：2007-10-25
申请号：US11308604
申请日：2006-04-11
申请人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
发明人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

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