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1. 发明申请

US20070249133A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 审中-公开
标题翻译：用于半导体器件的导电间隔物
公开(公告)号：US20070249133A1
公开(公告)日：2007-10-25
申请号：US11308604
申请日：2006-04-11
申请人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
发明人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

2. 发明申请

US20080272398A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 有权
标题翻译：用于半导体器件的导电间隔件和形成方法
公开(公告)号：US20080272398A1
公开(公告)日：2008-11-06
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/00
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

3. 发明授权

US08039888B2 Conductive spacers for semiconductor devices and methods of forming 有权
标题翻译：用于半导体器件的导电间隔件及其形成方法
公开(公告)号：US08039888B2
公开(公告)日：2011-10-18
申请号：US11848597
申请日：2007-08-31
申请人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
发明人： Gary Bela Bronner , David Michael Fried , Jeffrey Peter Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Y. Sardesai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

4. 发明授权

US06504210B1 Fully encapsulated damascene gates for Gigabit DRAMs 有权
标题翻译：用于千兆DRAM的全封装大马士革门
公开(公告)号：US06504210B1
公开(公告)日：2003-01-07
申请号：US09599484
申请日：2000-06-23
申请人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Jack A. Mandelman , Viraj Sardesai , Mary Elizabeth Weybright
发明人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Jack A. Mandelman , Viraj Sardesai , Mary Elizabeth Weybright
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/28044 , H01L27/10873 , H01L27/10876 , H01L27/10891 , H01L29/4941 , H01L29/6653 , H01L29/66553
摘要： A fully polysilicon encapsulated metal-containing damascene gate structure is provided that is useful in Gigabit DRAM (dynamic random access memory) device. The fully encapsulated metal-containing damascene gate comprises a semiconductor substrate having a gate oxide layer formed on a surface portion of said substrate; a gate polysilicon layer formed on said gate oxide layer; a metal layer formed on said polysilicon layer; and a cap oxide layer formed on said metal layer, wherein said metal layer is completely encapsulated by said polysilicon and oxide layers. The damascene gate structure may also include polysilicon spacers formed on said gate polysilicon layer and said metal layer is encapsulated therein and outer polysilicon sidewalls that are oxidized.
摘要翻译：提供了一种完全多晶硅封装的含金属镶嵌栅极结构，可用于千兆DRAM（动态随机存取存储器）器件。完全封装的含金属的镶嵌栅极包括具有形成在所述基板的表面部分上的栅极氧化层的半导体基板; 形成在所述栅极氧化物层上的栅极多晶硅层; 形成在所述多晶硅层上的金属层; 以及形成在所述金属层上的帽氧化层，其中所述金属层被所述多晶硅和氧化物层完全包封。镶嵌栅极结构还可以包括形成在所述栅极多晶硅层上的多晶硅间隔物，并且所述金属层被封装在其中，并且外部多晶硅侧壁被氧化。

5. 发明申请

US20110092056A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20110092056A1
公开(公告)日：2011-04-21
申请号：US12977134
申请日：2010-12-23
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/762 , H01L21/3205
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

6. 发明申请

US20080166857A1 ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT 有权
标题翻译：氧化铝层和集成电路下面形成的导电路径
公开(公告)号：US20080166857A1
公开(公告)日：2008-07-10
申请号：US11621699
申请日：2007-01-10
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

7. 发明授权

US08563398B2 Electrically conductive path forming below barrier oxide layer and integrated circuit 有权
标题翻译：阻挡氧化层下方的导电路径和集成电路
公开(公告)号：US08563398B2
公开(公告)日：2013-10-22
申请号：US12977134
申请日：2010-12-23
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L21/30
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

8. 发明授权

US07923840B2 Electrically conductive path forming below barrier oxide layer and integrated circuit 有权
标题翻译：阻挡氧化层下方的导电路径和集成电路
公开(公告)号：US07923840B2
公开(公告)日：2011-04-12
申请号：US11621699
申请日：2007-01-10
申请人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
发明人： Gregory Costrini , Ramachandra Divakaruni , Jeffrey P. Gambino , Randy W. Mann
IPC分类号： H01L23/48
CPC分类号： H01L21/28518 , H01L21/743 , H01L27/105 , H01L27/11 , H01L27/1203
摘要： Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.
摘要翻译：公开了在绝缘体上半导体（SOI）基板的阻挡氧化物层和包括该路径的集成电路之下形成导电路径的方法。在一个实施例中，该方法包括在绝缘体上半导体（SOI）衬底的阻挡氧化物层下方形成导电路径，该方法包括：在半导体衬底上形成第一阻挡氧化物层; 在所述第一阻挡氧化物层内形成所述导电路径; 以及在所述第一阻挡氧化物层上形成第二阻挡氧化物层。导电路径允许通过在SOI衬底上的阻挡氧化物层下形成布线路径来减小SRAM面积。

9. 发明授权

US06548357B2 Modified gate processing for optimized definition of array and logic devices on same chip 失效
标题翻译：改进的门处理，用于在同一芯片上优化阵列和逻辑器件的定义
公开(公告)号：US06548357B2
公开(公告)日：2003-04-15
申请号：US10117869
申请日：2002-04-08
申请人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
发明人： Mary E. Weybright , Gary Bronner , Richard A. Conti , Ramachandra Divakaruni , Jeffrey Peter Gambino , Peter Hoh , Uwe Schroeder
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/823456 , H01L27/1052 , H01L27/10873
摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.
摘要翻译：在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。这扩大了阵列栅极导体处理窗口。第二电介质盖层改善了支撑装置和阵列装置的线宽控制。在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

10. 发明授权

US06495876B1 DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS 失效
标题翻译： DRAM带：用于改善高密度沟槽DRAMS中的带状电阻的氢退火
公开(公告)号：US06495876B1
公开(公告)日：2002-12-17
申请号：US09609288
申请日：2000-06-30
申请人： Gary Bronner , Ramachandra Divakaruni , Yoichi Takegawa
发明人： Gary Bronner , Ramachandra Divakaruni , Yoichi Takegawa
IPC分类号： H01L27108
CPC分类号： H01L21/3003 , H01L27/10867
摘要： A method and structure for a DRAM device which includes a trench within an insulator, a conductor within the trench, a transistor adjacent a first side of the trench, and a shallow trench isolation region formed within a top portion of the conductor on a second side of the trench, opposite the first side, wherein the top portion of the conductor has a curved shape at an edge of the shallow trench isolation region. The curved shape comprises a conductive strap and electrically connects the conductor and the single crystal where the transistor is formed, further comprising a collar oxide surrounding the top portion of the conductor, the collar oxide controlling a shape and location of the curved shape. The curved shape is formed by hydrogen annealing, and may be convex, or concave. The DRAM further comprising a collar oxide extending into the shallow trench isolation region on the second side.
摘要翻译：一种用于DRAM器件的方法和结构，其包括绝缘体内的沟槽，沟槽内的导体，与沟槽的第一侧相邻的晶体管，以及形成在第二侧的导体的顶部内的浅沟槽隔离区所述沟槽的第一侧相对，其中所述导体的顶部在所述浅沟槽隔离区域的边缘处具有弯曲形状。弯曲形状包括导电带并且电连接导体和形成晶体管的单晶，还包括围绕导体顶部的环形氧化物，该环形氧化物控制弯曲形状的形状和位置。弯曲形状由氢退火形成，并且可以是凸形或凹形。 DRAM还包括延伸到第二侧上的浅沟槽隔离区域的环状氧化物。

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