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1. 发明授权

US07566652B2 Electrically inactive via for electromigration reliability improvement 有权
标题翻译：电气非活动通道，用于电迁移可靠性改进
公开(公告)号：US07566652B2
公开(公告)日：2009-07-28
申请号：US11491846
申请日：2006-07-24
申请人： Ki-Don Lee , Young-Joon Park , Ennis Takashi Ogawa
发明人： Ki-Don Lee , Young-Joon Park , Ennis Takashi Ogawa
IPC分类号： H01L21/20
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326. The isolated via 326 mitigates void formation and/or void migration during operation/conduction with electrons traveling from the first trench 316 to the second trench 318 via the metal line 304.
摘要翻译：半导体器件300包括形成在第一电介质层302中的金属线304.覆盖层306形成为金属线304.第二电介质层308形成在第一电介质层302和金属线304上。第一通孔 310形成在第二电介质层308中并与金属线304接触。第二通孔312形成在第二电介质层308中并与金属线304接触，并且与第一通孔310相距一定距离电绝缘通孔326形成在第二电介质层308中并与金属线304接触并且在第一通孔310和第二通孔312之间。第三电介质层314形成在第二介电层308上。首先并且第二沟槽316,318分别形成在第三电介质层314中并与第一通孔310和第二通孔312接触。隔离沟槽328形成在第三电介质层中并且与隔离通孔326接触。隔离通孔326可减少在从第一沟槽316行进到第二沟槽318的电子的操作/传导过程中的空隙形成和/或空隙迁移金属线304。

2. 发明申请

US20080017989A1 Electrically inactive via for electromigration reliability improvement 有权
标题翻译：电气非活动通道，用于电迁移可靠性改进
公开(公告)号：US20080017989A1
公开(公告)日：2008-01-24
申请号：US11491846
申请日：2006-07-24
申请人： Ki-Don Lee , Young-Joon Park , Ennis Takashi Ogawa
发明人： Ki-Don Lee , Young-Joon Park , Ennis Takashi Ogawa
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/522 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device 300 includes a metal line 304 formed in a first dielectric layer 302. A capping layer 306 is formed the metal line 304. A second dielectric layer 308 is formed over the first dielectric layer 302 and the metal line 304. A first via 310 is formed in the second dielectric layer 308 and in contact with the metal line 304. A second via 312 is formed in the second dielectric layer 308 and in contact with the metal line 304, and is positioned a distance away from the first via 310. An electrically isolated via 326 is formed in the second dielectric layer 308 and in contact with the metal line 304 and in between the first via 310 and the second via 312. A third dielectric layer 314 is formed over the second dielectric layer 308. First and second trenches 316, 318 are formed in the third dielectric layer 314 and in contact with the first via 310 and the second via 312, respectively. An isolated trench 328 is formed in the third dielectric layer and in contact with the isolated via 326. The isolated via 326 mitigates void formation and/or void migration during operation/conduction with electrons traveling from the first trench 316 to the second trench 318 via the metal line 304.
摘要翻译：半导体器件300包括形成在第一电介质层302中的金属线304.覆盖层306形成为金属线304.第二电介质层308形成在第一电介质层302和金属线304上。第一通孔 310形成在第二电介质层308中并与金属线304接触。第二通孔312形成在第二电介质层308中并与金属线304接触，并且与第一通孔310相距一定距离电绝缘通孔326形成在第二电介质层308中并与金属线304接触并且在第一通孔310和第二通孔312之间。第三电介质层314形成在第二介电层308上。首先并且第二沟槽316,318分别形成在第三电介质层314中并与第一通孔310和第二通孔312接触。隔离沟槽328形成在第三电介质层中并且与隔离通孔326接触。隔离通孔326可减少在从第一沟槽316行进到第二沟槽318的电子的操作/传导过程中的空隙形成和/或空隙迁移金属线304。

3. 发明授权

US09111779B2 IC resistor formed with integral heatsinking structure 有权
标题翻译：集成电阻形成整体散热结构
公开(公告)号：US09111779B2
公开(公告)日：2015-08-18
申请号：US12537994
申请日：2009-08-07
申请人： Young-Joon Park , Ki-Don Lee
发明人： Young-Joon Park , Ki-Don Lee
IPC分类号： H01L29/00 , H01L27/08 , H01L23/367 , H01L49/02 , H01L27/02
CPC分类号： H01L27/0802 , H01L23/367 , H01L27/0248 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.
摘要翻译：电阻器形成在场氧化物上，其中电阻体的一部分构造成与集成电路（IC）衬底中的有源区重叠，以提供电阻体的散热。在一个实施例中，冷却指状物从电阻体延伸超过场氧化物以与有源区重叠。在另一个实施例中，电阻体的次要区域与有源区重叠。电阻体可以由多晶硅（多晶硅），硅化多晶硅或金属形成。在电阻体的重叠部分和有源区域之间形成具有比场氧化物更高的导热性的氧化物。

4. 发明申请

US20100032770A1 IC RESISTOR FORMED WITH INTEGRAL HEATSINKING STRUCTURE 有权
标题翻译：具有整体热交换结构的IC电阻
公开(公告)号：US20100032770A1
公开(公告)日：2010-02-11
申请号：US12537994
申请日：2009-08-07
申请人： Young-Joon Park , Ki-Don Lee
发明人： Young-Joon Park , Ki-Don Lee
IPC分类号： H01L27/06 , H01L29/86 , H01L21/02
CPC分类号： H01L27/0802 , H01L23/367 , H01L27/0248 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A resistor is formed on field oxide with a portion of the resistor body configured to overlap an active region in an integrated circuit (IC) substrate to provide heatsinking for the resistor body. In one embodiment, cooling fingers extend from the resistor body beyond the field oxide to overlap the active region. In another embodiment, minor areas of the resistor body overlap the active region. The resistor body may be formed of polycrystalline silicon (polysilicon), silicided polysilicon, or metal. An oxide having greater thermal conductance than the field oxide is formed between the overlapping parts of the resistor body and the active region.
摘要翻译：电阻器形成在场氧化物上，其中电阻体的一部分构造成与集成电路（IC）衬底中的有源区重叠，以提供电阻体的散热。在一个实施例中，冷却指状物从电阻体延伸超过场氧化物以与有源区重叠。在另一个实施例中，电阻体的次要区域与有源区重叠。电阻体可以由多晶硅（多晶硅），硅化多晶硅或金属形成。在电阻体的重叠部分和有源区域之间形成具有比场氧化物更高的导热性的氧化物。

5. 发明授权

US09431343B1 Stacked damascene structures for microelectronic devices 有权
标题翻译：用于微电子器件的堆叠镶嵌结构
公开(公告)号：US09431343B1
公开(公告)日：2016-08-30
申请号：US14691336
申请日：2015-04-20
申请人： Ki-Don Lee , Jinseok Kim
发明人： Ki-Don Lee , Jinseok Kim
IPC分类号： H01L23/52 , H01L23/528 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5283 , H01L21/76838 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/58
摘要： A microelectronic device includes a dual-damascene interconnect structure and a single-damascene line structure directly on the dual-damascene interconnect structure. The dual-damascene interconnect structure and the single-damascene line structure may each include multiple line segments that are arranged in a brick wall pattern. The brick wall pattern may also be used with two or more single-damascene line structures. Various microelectronic devices and related fabrication methods are described.
摘要翻译：微电子器件包括双镶嵌互连结构和直接在双镶嵌互连结构上的单镶嵌线结构。双镶嵌互连结构和单镶嵌线结构可以各自包括以砖墙图案布置的多个线段。砖墙图案也可以与两个或更多个单镶嵌线结构一起使用。描述了各种微电子器件和相关的制造方法。

6. 发明授权

US07078817B2 Multiple copper vias for integrated circuit metallization 失效
标题翻译：用于集成电路金属化的多个铜通孔
公开(公告)号：US07078817B2
公开(公告)日：2006-07-18
申请号：US11010596
申请日：2004-12-13
申请人： Paul S. Ho , Ki-Don Lee , Ennis Ogawa , Hideki Matsuhashi
发明人： Paul S. Ho , Ki-Don Lee , Ennis Ogawa , Hideki Matsuhashi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
摘要翻译：可以减少集成电路的铜基金属化中的电迁移，该集成电路包括通过中间绝缘层将下面的导电线与覆盖的含铜线电连接的第一含铜通孔。通过形成至少第二含铜通孔，通过与第一含铜通孔平行地电连接下面的导电线路和覆盖的含铜线路穿过中间绝缘层，可以减少电迁移。多通道可以提供冗余以减少早期故障统计。此外，由于电流分布在通孔中，所以可以减少电迁移驱动力，并且可以减少在通孔接口处的空隙中的局部焦耳加热。因此，即使形成通孔，由于焦耳加热，结构也可能不会由于灾难性热失控而失效。

7. 发明授权

US06919639B2 Multiple copper vias for integrated circuit metallization and methods of fabricating same 失效
标题翻译：用于集成电路金属化的多个铜通孔及其制造方法
公开(公告)号：US06919639B2
公开(公告)日：2005-07-19
申请号：US10271284
申请日：2002-10-15
申请人： Paul S. Ho , Ki-Don Lee , Ennis Ogawa , Hideki Matsuhashi
发明人： Paul S. Ho , Ki-Don Lee , Ennis Ogawa , Hideki Matsuhashi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
摘要翻译：可以减少集成电路的铜基金属化中的电迁移，该集成电路包括通过中间绝缘层将下面的导电线与覆盖的含铜线电连接的第一含铜通孔。通过形成至少第二含铜通孔，通过与第一含铜通孔平行地电连接下面的导电线路和覆盖的含铜线路穿过中间绝缘层，可以减少电迁移。多通道可以提供冗余以减少早期故障统计。此外，由于电流分布在通孔中，所以可以减少电迁移驱动力，并且可以减少在通孔接口处的空隙中的局部焦耳加热。因此，即使形成通孔，由于焦耳加热，结构也可能不会由于灾难性热失控而失效。

8. 发明申请

US20050093163A1 Multiple copper vias for integrated circuit metallization 失效
标题翻译：用于集成电路金属化的多个铜通孔
公开(公告)号：US20050093163A1
公开(公告)日：2005-05-05
申请号：US11010596
申请日：2004-12-13
申请人： Paul Ho , Ki-Don Lee , Ennis Ogawa , Hideki Matsuhashi
发明人： Paul Ho , Ki-Don Lee , Ennis Ogawa , Hideki Matsuhashi
IPC分类号： H01L23/522 , H01L23/532 , H01L23/544 , H01L21/44 , H01L23/48 , H01L23/52
CPC分类号： H01L22/34 , H01L23/522 , H01L23/5226 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
摘要翻译：可以减少集成电路的铜基金属化中的电迁移，该集成电路包括通过中间绝缘层将下面的导电线与覆盖的含铜线电连接的第一含铜通孔。通过形成至少第二含铜通孔，通过与第一含铜通孔平行地电连接下面的导电线路和覆盖的含铜线路穿过中间绝缘层，可以减少电迁移。多通道可以提供冗余以减少早期故障统计。此外，由于电流分布在通孔中，所以可以减少电迁移驱动力，并且可以减少在通孔接口处的空隙中的局部焦耳加热。因此，即使形成通孔，由于焦耳加热，结构也可能不会由于灾难性热失控而失效。

9. 发明授权

US07031163B2 Mechanical cooling fin for interconnects 有权
标题翻译：用于互连的机械散热片
公开(公告)号：US07031163B2
公开(公告)日：2006-04-18
申请号：US10688288
申请日：2003-10-17
申请人： Ki-Don Lee , Srikanth Krishnan , William R. Hunter
发明人： Ki-Don Lee , Srikanth Krishnan , William R. Hunter
IPC分类号： H05K7/20 , H01L23/34
CPC分类号： H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.
摘要翻译：在一个实施例中，集成电路包括在具有顶表面和底表面的电介质层内的电活动互连线，介电层的底表面耦合到介电层下面的衬底的顶表面。电介质层具有水平布置的散热层。电绝缘导体或冷却翅片位于电介质层内的位于比所述有源互连线下方更靠近衬底的散热层处。电不活动的导体被耦合到所述电活动互连线作为电活动互连线的延伸部分以从其中散发热量。

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