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1. 发明授权

US07031163B2 Mechanical cooling fin for interconnects 有权
标题翻译：用于互连的机械散热片
公开(公告)号：US07031163B2
公开(公告)日：2006-04-18
申请号：US10688288
申请日：2003-10-17
申请人： Ki-Don Lee , Srikanth Krishnan , William R. Hunter
发明人： Ki-Don Lee , Srikanth Krishnan , William R. Hunter
IPC分类号： H05K7/20 , H01L23/34
CPC分类号： H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, an integrated circuit includes an electrically active interconnect line within a dielectric layer having a top and bottom surface, the bottom surface of the dielectric layer being coupled to the top surface of a substrate underlying the dielectric layer. The dielectric layer has horizontally arranged heat dissipating layers. An electrically inactive conductor or cooling fin is located within the dielectric layer at a heat dissipating layer below and closer to the substrate than said active interconnect line. The electrically inactive conductor is coupled to said electrically active interconnect line as an extensions of electrically active interconnect line to dissipate heat therefrom.
摘要翻译：在一个实施例中，集成电路包括在具有顶表面和底表面的电介质层内的电活动互连线，介电层的底表面耦合到介电层下面的衬底的顶表面。电介质层具有水平布置的散热层。电绝缘导体或冷却翅片位于电介质层内的位于比所述有源互连线下方更靠近衬底的散热层处。电不活动的导体被耦合到所述电活动互连线作为电活动互连线的延伸部分以从其中散发热量。

2. 发明授权

US4538343A Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking 失效
标题翻译：通道停止隔离技术利用两步蚀刻和选择性氧化与侧壁掩蔽
公开(公告)号：US4538343A
公开(公告)日：1985-09-03
申请号：US620995
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence Teng , William R. Hunter
发明人： Gordon P. Pollack , Clarence Teng , William R. Hunter
IPC分类号： H01L29/78 , H01L21/76 , H01L21/762 , H01L29/06 , H01L21/31
CPC分类号： H01L29/0638 , H01L21/76232 , H01L21/76237 , Y10S148/085 , Y10S148/117
摘要： A sidewall-nitride isolation technology avoids stress-induced defects, while permitting a heavy channel stop implant to avoid turn-on of the field oxide transistor, by performing a two-step silicon etch. The first channel stop implant is performed after the first silicon etch, before the sidewall nitride is deposited. A further silicon etch is performed after the sidewall nitride is in place, and a second channel stop implant follows. The first implant can be a light dose, to avoid excess subthreshold leakage in the active devices due to field-assisted turn on at the corners of the moat regions, and the second implant can be a very heavy dose to provide complete isolation without any danger of the channel stop species encroaching on the active device regions.
摘要翻译：通过执行两步硅蚀刻，侧壁氮化物隔离技术避免了应力引起的缺陷，同时允许重通道停止注入以避免场氧化物晶体管的导通。在第一硅蚀刻之后，在侧壁氮化物沉积之前执行第一通道停止注入。在侧壁氮化物就位之后进行另外的硅蚀刻，并且跟随第二通道停止注入。第一种植入物可以是轻剂量，以避免由于在护环区域的角落处的场辅助打开而导致的活动装置中的过度亚阈值泄漏，并且第二种植入物可以是非常重的剂量以提供完全隔离而没有任何危险的通道停止物种侵入有源器件区域。

3. 发明授权

US4300374A Key retaining cylinder for a lock 失效
标题翻译：用于锁的钥匙保持筒
公开(公告)号：US4300374A
公开(公告)日：1981-11-17
申请号：US61678
申请日：1979-07-30
申请人： Richard O. Mullich , William R. Hunter
发明人： Richard O. Mullich , William R. Hunter
IPC分类号： E05B11/00 , E05B27/00 , E05B65/06
CPC分类号： E05B11/00 , E05B27/00 , Y10S70/42 , Y10T70/5341 , Y10T70/7605 , Y10T70/7667 , Y10T70/7706 , Y10T70/7768
摘要： A key retaining cylinder for a lock operative on standard keys is disclosed. The cylinder of the lock includes an idler ring driven in rotation, with lost motion, by the lock plug. The idler ring is cooperatively disposed with respect to one of the pins so as to restrict the motion thereof when that lock has been used to lock the lock set and to not restrict the movement thereof when that lock has been used to unlock the lock set. Restricted movement of the pin together with the contrapment of the pin within the combinational notch of the key prevents removal of the key. Further features and embodiments are disclosed including provisions for symmetrical operation thereof for left-handed and right-handed doors.
摘要翻译：公开了一种用于在标准键上操作的锁的钥匙保持筒。锁的气缸包括通过锁定塞旋转驱动的空转环，并且由空转引起的运动。惰轮相对于其中一个销配合配置，以便当该锁被用于锁定锁定装置时限制其运动，并且当该锁已经用于解锁锁定装置时，不会限制其运动。销的限制运动与销的组合槽内的销的配合阻止了钥匙的移除。公开了另外的特征和实施例，其包括用于左手和右手门的对称操作的设置。

4. 发明授权

US06710443B1 INTEGRATED CIRCUIT PROVIDING THERMALLY CONDUCTIVE STRUCTURES SUBSTANTIALLY HORIZONTALLY COUPLED TO ONE ANOTHER WITHIN ONE OR MORE HEAT DISSIPATION LAYERS TO DISSIPATE HEAT FROM A HEAT GENERATING STRUCTURE 有权
标题翻译：集成电路在一个或多个散热层中大幅度地耦合到另一个热导电结构，以将热量从热生成结构中分离出来
公开(公告)号：US06710443B1
公开(公告)日：2004-03-23
申请号：US10326612
申请日：2002-12-20
申请人： Timothy A. Rost , William R. Hunter , Bradley S. Young
发明人： Timothy A. Rost , William R. Hunter , Bradley S. Young
IPC分类号： H01L2334
CPC分类号： H01L23/367 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311
摘要： In one embodiment, an integrated circuit includes a heat generating structure within a dielectric region and one or more substantially horizontally arranged heat dissipation layers within the dielectric region. Each heat dissipation layer includes electrically inactive thermally conductive structures, at least two such structures in at least one such layer being substantially horizontally connected and thermally coupled to one another within the layer. The electrically inactive thermally conductive structures cooperate to facilitate dissipation of heat from the heat generating structure. In another embodiment, an integrated circuit includes one or more heat generating structures within a dielectric region and electrically inactive thermal posts formed at least partially within the dielectric region. At least one such post is substantially horizontally connected and thermally coupled to another such post. The electrically inactive thermal posts cooperate to facilitate dissipation of heat from the one or more heat generating structures.
摘要翻译：在一个实施例中，集成电路包括电介质区域内的发热结构和电介质区域内的一个或多个基本水平布置的散热层。每个散热层包括电惰性导热结构，至少一个这样的层中的至少两个这样的结构基本上水平连接并且在该层内彼此热耦合。电惰性的导热结构协同作用以促进来自发热结构的热量的散发。在另一个实施例中，集成电路包括电介质区域内的一个或多个发热结构和至少部分地形成在电介质区域内的电活性热柱。至少一个这样的柱基本上水平连接并且热耦合到另一个这样的柱。电惰性的热柱配合以便于从一个或多个发热结构散发热量。

5. 发明授权

US4580330A Integrated circuit isolation 失效
标题翻译：集成电路隔离
公开(公告)号：US4580330A
公开(公告)日：1986-04-08
申请号：US621019
申请日：1984-06-15
申请人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
发明人： Gordon P. Pollack , Clarence W. Teng , William R. Hunter , Christopher Slawinski , Robert R. Doering
IPC分类号： H01L29/78 , H01L21/32 , H01L21/76 , H01L21/762 , H01L29/06
CPC分类号： H01L29/0638 , H01L21/32 , H01L21/76232 , Y10S148/05
摘要： An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.
摘要翻译：一种集成电路隔离技术，其中通过在将第二氮化物（防止侵入的侧壁氮化物）添加到第一氮化物（覆盖护城河区域）之前执行底切和回填来改进现有技术的氮化物 - 侧壁方法。因此，使两个氮化物之间的对接更牢固，并且不会发生在护环氮化物和侧壁氮化物之间的对接接合处的局部鸟鸣。

6. 发明授权

US5311098A Interference photocathode 失效
标题翻译：干涉光电阴极
公开(公告)号：US5311098A
公开(公告)日：1994-05-10
申请号：US888083
申请日：1992-05-26
申请人： John F. Seely , William R. Hunter
发明人： John F. Seely , William R. Hunter
IPC分类号： H01J1/34 , H01J43/08
CPC分类号： H01J1/34
摘要： An interference photocathode includes a reflective substrate and interference layers disposed on said reflective substrate for selectively enhancing a first photoelectric yield of said photocathode when irradiated by radiation having a first wavelength relative to a second photoelectric yield of said photocathode when irradiated by radiation having a second wavelength. In one embodiment, the interference layers include a dielectric layer having a wavelength dependent effective thickness disposed on said reflective substrate such that said effective thickness for radiation having said first wavelength is an odd multiple of a quarter of said first wavelength and said effective thickness for radiation having said second wavelength is an even multiple of a quarter of said second wavelength. In another embodiment, the dielectric layer includes a layer of electrically conductive material and a dielectric material disposed between said layer of electrically conductive material and said reflective substrate.
摘要翻译：干涉光电阴极包括反射基板和设置在所述反射基板上的干涉层，用于当用具有第二波长的辐射照射时相对于所述光电阴极的第二光电产量照射具有第一波长的辐射来选择性地增强所述光电阴极的第一光电收益。在一个实施例中，干涉层包括具有设置在所述反射基板上的波长相关有效厚度的电介质层，使得具有所述第一波长的辐射的所述有效厚度是所述第一波长的四分之一的奇数倍和所述辐射的有效厚度具有所述第二波长的是所述第二波长的四分之一的偶数倍。在另一个实施例中，电介质层包括导电材料层和设置在所述导电材料层和所述反射衬底之间的电介质材料。

7. 发明授权

US4356623A Fabrication of submicron semiconductor devices 失效
标题翻译：亚微米半导体器件的制造
公开(公告)号：US4356623A
公开(公告)日：1982-11-02
申请号：US187642
申请日：1980-09-15
申请人： William R. Hunter
发明人： William R. Hunter
IPC分类号： H01L21/033 , H01L29/08 , H01L29/78 , H01L21/22 , H01L21/26
CPC分类号： H01L29/78 , H01L21/0337 , H01L29/0847 , Y10S438/965
摘要： A method for fabricating a semiconductor device of relatively small scale. A conductivity layer is deposited on a substrate of a polarity. Regions of opposite polarity are partially formed on either side of the conductor layer. Vertical layers are formed to partially cover the regions of opposite polarity and are located adjacent to the conductor layer. Extensions of the regions of opposite polarity are formed such that a portion of the extension is defined by the location of the vertical layers.
摘要翻译：一种制造尺寸相对较小的半导体器件的方法。导电层沉积在极性的基底上。相反极性的区域部分地形成在导体层的任一侧上。形成垂直层以部分地覆盖相反极性的区域并且位于导体层附近。形成相反极性的区域的延伸部，使得延伸部分由垂直层的位置限定。

8. 发明授权

US4631803A Method of fabricating defect free trench isolation devices 失效
标题翻译：制造无缺陷沟槽隔离器件的方法
公开(公告)号：US4631803A
公开(公告)日：1986-12-30
申请号：US701465
申请日：1985-02-14
申请人： William R. Hunter , Christopher Slawinski , Clarence W. Teng
发明人： William R. Hunter , Christopher Slawinski , Clarence W. Teng
IPC分类号： H01L21/762 , H01L21/763 , H01L21/302 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/76224 , H01L21/763 , Y10S148/05 , Y10S148/085 , Y10S148/117
摘要： The specification discloses an isolation trench (36) formed in a semiconductor body. A stress relief layer (38) of oxide is formed on the interior walls of the trench (36), the layer (38) being sufficiently thin to prevent stressing of the lower corners of the trench (36). A masking layer (40) of nitride is formed over the layer (38). An isolation body (42) of oxide or polysilicon then refills the remainder of the trench and a cap oxide (43) and layer (44) of field oxide is formed over the semiconductor body and the filled trench.
摘要翻译：该说明书公开了形成在半导体本体中的隔离沟槽（36）。在沟槽（36）的内壁上形成有氧化物的应力消除层（38），该层（38）足够薄以防止沟槽（36）的下角受到应力。在层（38）之上形成氮化物的掩模层（40）。然后，氧化物或多晶硅的隔离体（42）再补充沟槽的其余部分，半导体主体和填充沟槽上形成氧化膜（43）和场氧化物层（44）。

9. 发明授权

US4462689A Wide band scanning monochromator 失效
标题翻译：宽带扫描单色仪
公开(公告)号：US4462689A
公开(公告)日：1984-07-31
申请号：US398090
申请日：1982-07-09
申请人： Milton N. Kabler , Richard T. Williams , Jack C. Rife , William R. Hunter , Johnny P. Kirkland , Neil C. Lien
发明人： Milton N. Kabler , Richard T. Williams , Jack C. Rife , William R. Hunter , Johnny P. Kirkland , Neil C. Lien
IPC分类号： G01J3/18 , G21K1/06
CPC分类号： G21K1/06 , G01J3/18
摘要： A scanning monochromator is disclosed which is capable of operation over a wide bandwidth in an ultra-high vacuum. The monochromator includes a pair of carousel assemblies carrying the optical elements which may be independently positioned translationally along the optical axis of the instrument and also rotationally, which each positioning control operable from outside of the instrument. A carousel on each of the carousel assemblies carries several optical elements and is rotatable to change which optical element is used, also from outside of the instrument.
摘要翻译：公开了能够在超高真空下在宽带宽下工作的扫描单色仪。单色仪包括一对传送带组件，其携带光学元件，其可以沿着仪器的光轴平行地单独定位，并且还可旋转地，每个定位控制器可从仪器的外部操作。每个转盘组件上的转盘带有几个光学元件，并且也可以从仪器的外部旋转以改变使用哪个光学元件。

10. 发明授权

US4331708A Method of fabricating narrow deep grooves in silicon 失效
标题翻译：在硅中制造窄深槽的方法
公开(公告)号：US4331708A
公开(公告)日：1982-05-25
申请号：US203842
申请日：1980-11-04
申请人： William R. Hunter
发明人： William R. Hunter
IPC分类号： H01L21/308 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/308 , H01L21/76232 , Y10S148/051 , Y10S148/085 , Y10S148/111
摘要： A method of fabricating deep grooves having submicron widths in a semiconductor substrate. A pattern of submicron oxidation masking elements formed on the substrate surface serves as an oxidation mask for a thick oxide layer. After forming the oxide layer, the insulating elements are removed to form a pattern of submicron width openings in the oxide extending to the substrate. A selective anisotropic dry etch is then used to form deep, narrow grooves in the substrate conforming to the pattern of openings which are filled with an insulating material formed by thermal oxidation, chemical vapor deposition, or a combination thereof. This process is used to provide deep dielectric isolation between active areas in high density integrated circuits.
摘要翻译：一种在半导体衬底中制造具有亚微米宽度的深槽的方法。形成在基板表面上的亚微米氧化掩模元件的图案用作厚氧化物层的氧化掩模。在形成氧化物层之后，去除绝缘元件以在延伸到衬底的氧化物中形成亚微米宽度开口的图案。然后使用选择性各向异性干蚀刻在衬底中形成符合开口图案的深的窄槽，其填充有通过热氧化，化学气相沉积或其组合形成的绝缘材料。该过程用于在高密度集成电路中的有源区之间提供深电介质隔离。

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