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    • 3. 发明申请
    • POWER AMPLIFIER
    • 功率放大器
    • US20120025907A1
    • 2012-02-02
    • US13024144
    • 2011-02-09
    • Bon Hoon KOOKi Yong SONSong Cheol HONGGyu Suck KIMYoo Sam Na
    • Bon Hoon KOOKi Yong SONSong Cheol HONGGyu Suck KIMYoo Sam Na
    • H03G3/20
    • H03F1/0266H03F3/195H03F2200/105H03F2200/555
    • There is provided a power amplifier capable of supplying variable bias to an amplifier circuit by accurately transferring the envelope components of an input signal during the supply of active bias power to the amplifier circuit. The power amplifier includes: an envelope detector detecting an envelope of an input signal; a bias power generator including at least one P-type MOSFET and one N-type MOSFET connected to each other in an inverter manner between a driving power terminal supplying driving power having a preset voltage level and a reference bias power terminal supplying preset reference bias power to generate bias power varied according to detection results from the envelope detector; and an amplifier amplifying the input signal according to the bias power level from the bias power generator.
    • 提供了一种功率放大器,其能够通过在将有源偏置功率提供给放大器电路期间精确地传送输入信号的包络分量来向放大器电路提供可变偏置。 功率放大器包括:检测输入信号的包络的包络检测器; 一个偏置功率发生器,它包括至少一个P型MOSFET和一个N型MOSFET,它们以一个反相器的方式相互连接,驱动电源端子提供具有预设电压电平的驱动电源和一个提供预设参考偏置功率的参考偏置电源端子 以产生根据来自包络检测器的检测结果而变化的偏置功率; 以及根据偏置功率发生器的偏置功率电平放大输入信号的放大器。
    • 5. 发明申请
    • POWER AMPLIFIER MODULE HAVING BIAS CIRCUIT
    • 具有偏置电路的功率放大器模块
    • US20130076447A1
    • 2013-03-28
    • US13444491
    • 2012-04-11
    • Gyu Suck KIMYoo Sam NA
    • Gyu Suck KIMYoo Sam NA
    • H03F3/21
    • H03F1/304
    • There is provided a power amplifier module having a bias circuit, in which a bias power is supplied to an amplifier by differently setting an impedance between an input signal terminal and a reference power terminal and an impedance between the input signal terminal and a ground. The power amplifier module includes: an amplifier unit receiving a bias power to amplify an input signal; and a bias unit supplying the bias power to the amplifier, by differently setting an impedance between an input signal terminal transmitting the input signal therethrough and a reference power terminal transmitting a reference power having a predetermined voltage level and an impedance between the input signal terminal and a ground.
    • 提供了一种具有偏置电路的功率放大器模块,其中通过不同地设置输入信号端子和参考电源端子之间的阻抗以及输入信号端子和地之间的阻抗来将偏置功率提供给放大器。 功率放大器模块包括:放大器单元,接收偏置功率以放大输入信号; 以及偏置单元,通过不同地设置发送所述输入信号的输入信号端之间的阻抗和发送具有预定电压电平的参考功率的参考电源端子和所述输入信号端子和 一个地面。
    • 7. 发明申请
    • POWER AMPLIFIER
    • 功率放大器
    • US20110156817A1
    • 2011-06-30
    • US12712071
    • 2010-02-24
    • Hyeon Seok HWANGYoo Sam NAMoon Suk JEONGGyu Suck KIMByeong Hak JO
    • Hyeon Seok HWANGYoo Sam NAMoon Suk JEONGGyu Suck KIMByeong Hak JO
    • H03F3/16
    • H03F1/223
    • Disclosed herein is a power amplifier. The power amplifier includes a first common source transistor for amplifying an input signal into a predetermined level, a second common source transistor for compensating for input capacitance and performing auxiliary amplification for the first common source transistor, and a common gate transistor connected to the first common source transistor in a cascode structure, configured to be connected in parallel to the second common source transistor and prevent the first common source transistor from breaking down, and configured to output a signal amplified by a value obtained by adding the gain of the first common source transistor and the gain of the second common source transistor to each other.
    • 这里公开了功率放大器。 功率放大器包括用于将输入信号放大到预定电平的第一公共源极晶体管,用于补偿输入电容并对第一公共源晶体管执行辅助放大的第二公共源极晶体管,以及连接到第一公共栅极晶体管的公共栅晶体管 源极晶体管,其被配置为并联连接到第二公共源极晶体管,并且防止第一公共源极晶体管分解,并且被配置为输出通过将第一公共源的增益相加而获得的值放大的信号 晶体管和第二公共源极晶体管的增益。
    • 10. 发明申请
    • DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY
    • 数字相位锁定环路,减少环路延迟
    • US20110133795A1
    • 2011-06-09
    • US12790242
    • 2010-05-28
    • Gyu Suck KIMSeong Hwan CHOWoo Kon SON
    • Gyu Suck KIMSeong Hwan CHOWoo Kon SON
    • H03L7/08
    • H03L7/1806H03L2207/50
    • There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.
    • 提供了数字锁相环。 根据本发明的一个方面的数字锁相环可以包括:参考相位累积单元,输出参考采样相位值; 检测相位差信号的相位检测单元; 数字环路滤波器对来自相位检测单元的相位差信号进行滤波和平均; 产生具有预定频率的振荡信号的数字控制振荡器; DOC相位累积单元输出DCO采样相位值,并且产生具有以相继方式延迟的相同频率和不同相位的多个第一至第n个D-FF; 以及包括在相位检测单元,数字环路滤波器,数字控制振荡器和DOC相位累积单元的闭环中的第一至第N-D-FF,并且根据多个第一至第n时钟 分别来自DCO相位累积单元的信号。