专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130162350A1 POWER AMPLIFIER 有权
标题翻译：功率放大器
公开(公告)号：US20130162350A1
公开(公告)日：2013-06-27
申请号：US13407382
申请日：2012-02-28
申请人： Ki Yong SON , Gyu Suck KIM , Yoo Sam NA , Song Cheol Hong , Bon Hoon KOO
发明人： Ki Yong SON , Gyu Suck KIM , Yoo Sam NA , Song Cheol Hong , Bon Hoon KOO
IPC分类号： H03F3/68
CPC分类号： H03F1/3241 , H03F3/211 , H03F2200/336 , H03F2200/408
摘要： There is provided a power amplifier capable of increasing linear output power and efficiency without sacrificing an overall gain by employing a vector modulation function in a driving stage, with no separate vector modulator. The power amplifier includes a driving stage performing vector-modulation on an input RF signal to provide an I channel signal and a Q channel signal having different phases and amplifying the I channel signal and the Q channel signal to set gains; and a power stage amplifying power levels of the signals amplified by the driving stage.
摘要翻译：提供了一种功率放大器，其能够通过在驱动级中采用矢量调制功能而不牺牲整体增益来提高线性输出功率和效率，而没有单独的矢量调制器。功率放大器包括对输入RF信号执行向量调制以提供I信道信号和具有不同相位的Q信道信号的驱动级，并且放大I信道信号和Q信道信号以设置增益; 以及功率级放大由驱动级放大的信号的功率电平。

2. 发明申请

US20110304395A1 POWER AMPLIFIER 审中-公开
标题翻译：功率放大器
公开(公告)号：US20110304395A1
公开(公告)日：2011-12-15
申请号：US13006920
申请日：2011-01-14
申请人： Bon Hoon KOO , Ki Yong SON , Song Cheol HONG , Gyu Suck KIM , Yoo Sam NA
发明人： Bon Hoon KOO , Ki Yong SON , Song Cheol HONG , Gyu Suck KIM , Yoo Sam NA
IPC分类号： H03F3/45 , H03F3/68 , H03F1/22 , H03F3/16
CPC分类号： H03F3/195 , H03F1/0261 , H03F1/223 , H03F3/211 , H03F3/245 , H03F3/45179 , H03F2200/06 , H03F2200/09 , H03F2200/18 , H03F2200/451
摘要： Disclosed is a power amplifier. A power amplifier according to an aspect of the invention may include: a first amplification section having a first N metal oxide semiconductor (MOS) amplifier and a second N MOS amplifier connected in a cascode configuration and amplifying an input signal; a second amplification section having a first P MOS amplifier and a second P MOS amplifier connected in a cascode configuration and amplifying the input signal; and a power combining section combining respective output signals of the first amplification section and the second amplification section.
摘要翻译：公开了一种功率放大器。根据本发明的一个方面的功率放大器可以包括：第一放大部分，具有第一N个金属氧化物半导体（MOS）放大器和以共源共极配置连接并放大输入信号的第二N个MOS放大器; 第二放大部分，具有第一P MOS放大器和以共源共享配置连接的第二P MOS放大器，并放大输入信号; 以及组合第一放大部分和第二放大部分的输出信号的功率合并部分。

3. 发明申请

US20120025907A1 POWER AMPLIFIER 有权
标题翻译：功率放大器
公开(公告)号：US20120025907A1
公开(公告)日：2012-02-02
申请号：US13024144
申请日：2011-02-09
申请人： Bon Hoon KOO , Ki Yong SON , Song Cheol HONG , Gyu Suck KIM , Yoo Sam Na
发明人： Bon Hoon KOO , Ki Yong SON , Song Cheol HONG , Gyu Suck KIM , Yoo Sam Na
IPC分类号： H03G3/20
CPC分类号： H03F1/0266 , H03F3/195 , H03F2200/105 , H03F2200/555
摘要： There is provided a power amplifier capable of supplying variable bias to an amplifier circuit by accurately transferring the envelope components of an input signal during the supply of active bias power to the amplifier circuit. The power amplifier includes: an envelope detector detecting an envelope of an input signal; a bias power generator including at least one P-type MOSFET and one N-type MOSFET connected to each other in an inverter manner between a driving power terminal supplying driving power having a preset voltage level and a reference bias power terminal supplying preset reference bias power to generate bias power varied according to detection results from the envelope detector; and an amplifier amplifying the input signal according to the bias power level from the bias power generator.
摘要翻译：提供了一种功率放大器，其能够通过在将有源偏置功率提供给放大器电路期间精确地传送输入信号的包络分量来向放大器电路提供可变偏置。功率放大器包括：检测输入信号的包络的包络检测器; 一个偏置功率发生器，它包括至少一个P型MOSFET和一个N型MOSFET，它们以一个反相器的方式相互连接，驱动电源端子提供具有预设电压电平的驱动电源和一个提供预设参考偏置功率的参考偏置电源端子以产生根据来自包络检测器的检测结果而变化的偏置功率; 以及根据偏置功率发生器的偏置功率电平放大输入信号的放大器。

4. 发明申请

US20120007674A1 POWER AMPLIFIER REDUCING GAIN MISMATCH 审中-公开
标题翻译：功率放大器降低增益误差
公开(公告)号：US20120007674A1
公开(公告)日：2012-01-12
申请号：US13020273
申请日：2011-02-03
申请人： Ki Yong SON , Bon Hoon KOO , Song Cheol HONG , Gyu Suck KIM , Yoo Sam NA
发明人： Ki Yong SON , Bon Hoon KOO , Song Cheol HONG , Gyu Suck KIM , Yoo Sam NA
IPC分类号： H03F3/45
CPC分类号： H03F3/245 , H03F1/56 , H03F3/189 , H03F3/193 , H03F3/211 , H03F3/45179 , H03F2200/204 , H03F2200/222 , H03F2200/387 , H03F2200/405 , H03F2203/45562 , H03F2203/45644
摘要： There is provided a power amplifier reducing a gain mismatch in order to reduce a gain mismatch between an N MOS amplifier and a P MOS amplifier by cross-connecting outputs from a two-stage amplification unit in a power amplifier having amplification units with a stacked structure in which the N MOS amplifier and the P MOS amplifier are connected in series with each other.
摘要翻译：提供了一种减小增益失配的功率放大器，以便通过将具有堆叠结构的放大单元的功率放大器中的两级放大单元的输出交叉连接来减小N MOS放大器和P MOS放大器之间的增益失配其中N MOS放大器和P MOS放大器彼此串联连接。

5. 发明申请

US20130076447A1 POWER AMPLIFIER MODULE HAVING BIAS CIRCUIT 有权
标题翻译：具有偏置电路的功率放大器模块
公开(公告)号：US20130076447A1
公开(公告)日：2013-03-28
申请号：US13444491
申请日：2012-04-11
申请人： Gyu Suck KIM , Yoo Sam NA
发明人： Gyu Suck KIM , Yoo Sam NA
IPC分类号： H03F3/21
CPC分类号： H03F1/304
摘要： There is provided a power amplifier module having a bias circuit, in which a bias power is supplied to an amplifier by differently setting an impedance between an input signal terminal and a reference power terminal and an impedance between the input signal terminal and a ground. The power amplifier module includes: an amplifier unit receiving a bias power to amplify an input signal; and a bias unit supplying the bias power to the amplifier, by differently setting an impedance between an input signal terminal transmitting the input signal therethrough and a reference power terminal transmitting a reference power having a predetermined voltage level and an impedance between the input signal terminal and a ground.
摘要翻译：提供了一种具有偏置电路的功率放大器模块，其中通过不同地设置输入信号端子和参考电源端子之间的阻抗以及输入信号端子和地之间的阻抗来将偏置功率提供给放大器。功率放大器模块包括：放大器单元，接收偏置功率以放大输入信号; 以及偏置单元，通过不同地设置发送所述输入信号的输入信号端之间的阻抗和发送具有预定电压电平的参考功率的参考电源端子和所述输入信号端子和一个地面。

6. 发明申请

US20130057349A1 CMOS POWER AMPLIFIER 有权
标题翻译： CMOS功率放大器
公开(公告)号：US20130057349A1
公开(公告)日：2013-03-07
申请号：US13223738
申请日：2011-09-01
申请人： Byeong Hak JO , Yoo Sam NA , Hyeon Seok HWANG , Moon Suk JEONG , Gyu Suck KIM , Moon Sun KIM
发明人： Byeong Hak JO , Yoo Sam NA , Hyeon Seok HWANG , Moon Suk JEONG , Gyu Suck KIM , Moon Sun KIM
IPC分类号： H03F3/21 , H03F1/22
CPC分类号： H03F1/3205 , H03F1/223 , H03F3/211 , H03F2200/108 , H03F2200/18
摘要： There is provided a complementary metal oxide semiconductor (CMOS) power amplifier including: a load unit connected between an operating voltage supply terminal and an output terminal; an amplifying unit formed as a cascode structure between the load unit and a ground, amplifying a power of an input signal input through an input terminal and outputting the amplified signal through an output terminal; and a threshold voltage control unit varying a threshold voltage of the amplifying unit according to a magnitude of the input signal input through the input terminal.
摘要翻译：提供了一种互补金属氧化物半导体（CMOS）功率放大器，包括：连接在工作电压源端子和输出端子之间的负载单元; 放大单元，其形成为负载单元和地之间的共源共栅结构，放大通过输入端输入的输入信号的功率，并通过输出端输出放大的信号; 以及阈值电压控制单元，根据通过输入端子输入的输入信号的大小来改变放大单元的阈值电压。

7. 发明申请

US20110156817A1 POWER AMPLIFIER 有权
标题翻译：功率放大器
公开(公告)号：US20110156817A1
公开(公告)日：2011-06-30
申请号：US12712071
申请日：2010-02-24
申请人： Hyeon Seok HWANG , Yoo Sam NA , Moon Suk JEONG , Gyu Suck KIM , Byeong Hak JO
发明人： Hyeon Seok HWANG , Yoo Sam NA , Moon Suk JEONG , Gyu Suck KIM , Byeong Hak JO
IPC分类号： H03F3/16
CPC分类号： H03F1/223
摘要： Disclosed herein is a power amplifier. The power amplifier includes a first common source transistor for amplifying an input signal into a predetermined level, a second common source transistor for compensating for input capacitance and performing auxiliary amplification for the first common source transistor, and a common gate transistor connected to the first common source transistor in a cascode structure, configured to be connected in parallel to the second common source transistor and prevent the first common source transistor from breaking down, and configured to output a signal amplified by a value obtained by adding the gain of the first common source transistor and the gain of the second common source transistor to each other.
摘要翻译：这里公开了功率放大器。功率放大器包括用于将输入信号放大到预定电平的第一公共源极晶体管，用于补偿输入电容并对第一公共源晶体管执行辅助放大的第二公共源极晶体管，以及连接到第一公共栅极晶体管的公共栅晶体管源极晶体管，其被配置为并联连接到第二公共源极晶体管，并且防止第一公共源极晶体管分解，并且被配置为输出通过将第一公共源的增益相加而获得的值放大的信号晶体管和第二公共源极晶体管的增益。

8. 发明申请

US20070120611A1 Phase frequency detector capable of improving noise characteristics 失效
标题翻译：相位检波器能够改善噪声特性
公开(公告)号：US20070120611A1
公开(公告)日：2007-05-31
申请号：US11549046
申请日：2006-10-12
申请人： Yoo Hwan KIM , Ki Sung KWON , Soo Woong LEE , Jin Taek LEE , Yo Sub MOON , Sung Cheol SHIN , Gyu Suck KIM
发明人： Yoo Hwan KIM , Ki Sung KWON , Soo Woong LEE , Jin Taek LEE , Yo Sub MOON , Sung Cheol SHIN , Gyu Suck KIM
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03D13/003 , H03D13/004 , H03L7/085 , H03L7/18
摘要： A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.
摘要翻译：公开了一种用于改善PLL的带内相位噪声特性的相位频率检测器。相位频率检测器将参考频率与通过将压控振荡器（VCO）的输出频率除以预定分频比而产生的分频，将与基准频率和分频之间的相位差相对应的相位差信号进行比较频率，并改善噪声特性。

9. 发明申请

US20090280762A1 HIGH-ORDER HARMONIC REJECTION MIXER USING CURRENT STEERING TECHNIQUE 审中-公开
标题翻译：使用电流转向技术的高阶谐波抑制混频器
公开(公告)号：US20090280762A1
公开(公告)日：2009-11-12
申请号：US12259619
申请日：2008-10-28
申请人： Kyoung Seok PARK , Nam Heung KIM , Jeong Ki CHOI , Yo Sub MOON , Gyu Suck KIM , Seung Won SEO , Yoo Hwan KIM
发明人： Kyoung Seok PARK , Nam Heung KIM , Jeong Ki CHOI , Yo Sub MOON , Gyu Suck KIM , Seung Won SEO , Yoo Hwan KIM
IPC分类号： H04B1/16
CPC分类号： H03D7/1441 , H03D7/1483 , H03D2200/0043 , H03D2200/0086
摘要： A mixer includes, an input current generation unit generating an input current; a first path circuit unit including n number of transistors having sources connected in common to an output node of the input current generation unit; and a second path circuit unit including n number of transistors having sources connected in common to the output node of the input current generation unit, and respectively corresponding to the n number of transistors included in the first path circuit unit. Local oscillator signals sequentially phase-shifted by 180°/n are individually input to gates of the n number of transistors included in the first path circuit unit, and local oscillator signals having opposite phases to the local oscillator signals input to the gates of the corresponding transistors included in the first path circuit unit are individually input to gates of the n number of transistors included in the second path circuit unit.
摘要翻译：混合器包括：输入电流产生单元，其产生输入电流; 包括n个晶体管的第一路径电路单元，其源极共同连接到输入电流产生单元的输出节点; 以及第二路径电路单元，其包括n个晶体管，其源极共同连接到输入电流产生单元的输出节点，并且分别对应于包括在第一路径电路单元中的n个晶体管。顺序相移180°/ n的本地振荡器信号被分别输入到包括在第一路径电路单元中的n个晶体管的栅极，并且与本地振荡器信号相反的本地振荡器信号输入到相应的门包括在第一路径电路单元中的晶体管被单独地输入到包括在第二路径电路单元中的n个晶体管的栅极。

10. 发明申请

US20110133795A1 DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY 审中-公开
标题翻译：数字相位锁定环路，减少环路延迟
公开(公告)号：US20110133795A1
公开(公告)日：2011-06-09
申请号：US12790242
申请日：2010-05-28
申请人： Gyu Suck KIM , Seong Hwan CHO , Woo Kon SON
发明人： Gyu Suck KIM , Seong Hwan CHO , Woo Kon SON
IPC分类号： H03L7/08
CPC分类号： H03L7/1806 , H03L2207/50
摘要： There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.
摘要翻译：提供了数字锁相环。根据本发明的一个方面的数字锁相环可以包括：参考相位累积单元，输出参考采样相位值; 检测相位差信号的相位检测单元; 数字环路滤波器对来自相位检测单元的相位差信号进行滤波和平均; 产生具有预定频率的振荡信号的数字控制振荡器; DOC相位累积单元输出DCO采样相位值，并且产生具有以相继方式延迟的相同频率和不同相位的多个第一至第n个D-FF; 以及包括在相位检测单元，数字环路滤波器，数字控制振荡器和DOC相位累积单元的闭环中的第一至第N-D-FF，并且根据多个第一至第n时钟分别来自DCO相位累积单元的信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式