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1. 发明申请

US20080166887A1 Method of Depositing Thin Film and Method of Manufacturing Semiconductor Using the Same 有权
标题翻译：沉积薄膜的方法及使用其制造半导体的方法
公开(公告)号：US20080166887A1
公开(公告)日：2008-07-10
申请号：US11720450
申请日：2005-11-28
申请人： Ki Hoon Lee , Young Hoon Park , Sahng Kyoo Lee , Tae Wook Seo , Ho Seung Chang
发明人： Ki Hoon Lee , Young Hoon Park , Sahng Kyoo Lee , Tae Wook Seo , Ho Seung Chang
IPC分类号： H01L21/31
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/3146 , Y10S438/952
摘要： Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a) depositing an carbon anti-reflective film on the bottom film of a substrate; and (b) adding a compound containing nitrogen (N), fluorine (F) or silicon (Si) to the surface or the inner portion of the carbon anti-reflective film, to deposit a thin film of a-C:N, a-C:F or a-C:Si, having high selectivity, to a thickness from 1 to 100 nm using an atomic layer deposition process. Therefore, an ultrathin film having etching resistance is formed on or in the carbon anti-reflective film and the density and compressive stress of the carbon anti-reflective film are increased, thus increasing etching selectivity.
摘要翻译：本文公开了一种沉积薄膜的方法和使用该薄膜的半导体的制造方法，通过增加抗蚀性而具有高选择性，同时将与抗反射性相关联的消光系数保持为低。根据本发明的沉积薄膜的方法包括（a）在基底的底膜上沉积碳抗反射膜; 和（b）在碳抗反射膜的表面或内部添加含有氮（N），氟（F）或硅（Si）的化合物，沉积a：N，aC：F 或aC：Si，具有高选择性，使用原子层沉积工艺，厚度为1至100nm。因此，在碳抗反射膜上或碳抗反射膜上形成具有耐腐蚀性的超薄膜，并且碳抗反射膜的密度和压缩应力增加，从而增加蚀刻选择性。

2. 发明授权

US07842606B2 Method of depositing thin film and method of manufacturing semiconductor using the same 有权
标题翻译：沉积薄膜的方法和使用其制造半导体的方法
公开(公告)号：US07842606B2
公开(公告)日：2010-11-30
申请号：US11720450
申请日：2005-11-28
申请人： Ki Hoon Lee , Young Hoon Park , Sahng Kyoo Lee , Tae Wook Seo , Ho Seung Chang
发明人： Ki Hoon Lee , Young Hoon Park , Sahng Kyoo Lee , Tae Wook Seo , Ho Seung Chang
IPC分类号： H01L21/4763 , H01L21/02
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/3146 , Y10S438/952
摘要： Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a) depositing an carbon anti-reflective film on the bottom film of a substrate; and (b) adding a compound containing nitrogen (N), fluorine (F) or silicon (Si) to the surface or the inner portion of the carbon anti-reflective film, to deposit a thin film of a-C:N, a-C:F or a-C:Si, having high selectivity, to a thickness from 1 to 100 nm using an atomic layer deposition process. Therefore, an ultrathin film having etching resistance is formed on or in the carbon anti-reflective film and the density and compressive stress of the carbon anti-reflective film are increased, thus increasing etching selectivity.
摘要翻译：本文公开了一种沉积薄膜的方法和使用该薄膜的半导体的制造方法，通过增加抗蚀性而具有高选择性，同时将与抗反射性相关联的消光系数保持为低。根据本发明的沉积薄膜的方法包括（a）在基底的底膜上沉积碳抗反射膜; 和（b）在碳抗反射膜的表面或内部添加含有氮（N），氟（F）或硅（Si）的化合物，沉积a：N，aC：F 或aC：Si，具有高选择性，使用原子层沉积工艺，厚度为1至100nm。因此，在碳抗反射膜上或碳抗反射膜上形成具有耐腐蚀性的超薄膜，并且碳抗反射膜的密度和压缩应力增加，从而增加蚀刻选择性。

3. 发明授权

US07785664B2 Method of depositing thin film 失效
标题翻译：沉积薄膜的方法
公开(公告)号：US07785664B2
公开(公告)日：2010-08-31
申请号：US11571547
申请日：2005-12-14
申请人： Tae Wook Seo , Young Hoon Park , Ki Hoon Lee , Sahng Kyoo Lee
发明人： Tae Wook Seo , Young Hoon Park , Ki Hoon Lee , Sahng Kyoo Lee
IPC分类号： C23C16/06 , C23C16/34
CPC分类号： H01L21/76843 , H01L21/28556 , H01L21/76861
摘要： A method is provided for depositing thin films in which the thin films are continuously deposited into one chamber and 1-6 wafers are loaded into the chamber. In the method, a process gap between a shower head or a gas injection unit and a substrate is capable of being controlled. The method comprises (a) loading at least one substrate into the chamber, (b) depositing the Ti thin film onto the substrate, adjusted so that a first process gap is maintained, (c) moving a wafer block so that the first process gap is changed into a second process gap in order to control the process gap of the substrate upon which the Ti thin film is deposited, (d) depositing the TiN thin film onto the substrate, moved to set the second process gap, and (e) unloading the substrate upon which the Ti/TiN thin films are deposited.
摘要翻译：提供了一种用于沉积薄膜的方法，其中薄膜连续沉积到一个室中，并且将1-6个晶片装入室中。在该方法中，能够控制淋浴喷头或气体喷射单元与基板之间的处理间隙。该方法包括：（a）将至少一个衬底装载到腔室中，（b）将Ti薄膜沉积到衬底上，进行调整，使得保持第一工艺间隙;（c）移动晶片块使得第一工艺间隙改变为第二工艺间隙，以便控制沉积Ti薄膜的衬底的工艺间隙，（d）将TiN薄膜沉积到衬底上，移动以设定第二工艺间隙，（e）卸载沉积有Ti / TiN薄膜的基板。

4. 发明授权

US07253101B2 Deposition method of TiN thin film having a multi-layer structure 有权
标题翻译：具有多层结构的TiN薄膜的沉积方法
公开(公告)号：US07253101B2
公开(公告)日：2007-08-07
申请号：US11205990
申请日：2005-08-17
申请人： Young Hoon Park , Sahng Kyoo Lee , Tae Wook Seo
发明人： Young Hoon Park , Sahng Kyoo Lee , Tae Wook Seo
IPC分类号： H01L21/4763
CPC分类号： H01L21/02186 , C23C16/34 , C23C16/45523 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/3141 , H01L21/318 , H01L21/76846
摘要： Provided is a method of depositing a metal nitride film having a multilayer structure and different deposition speeds on a substrate. The method is performed by forming a first lower metal nitride film on the substrate at a first deposition speed, forming a second lower metal nitride film on the first lower metal nitride film at a second deposition speed, and forming an upper metal nitride film having a large content of nitrogen (N) on a lower TiN film which is formed by the forming of the first lower metal nitride film and the second lower metal nitride film, at a third deposition speed, to improve stability with respect to exposure to air/moisture. The deposition speed of the metal nitride film having a multi-layer structure satisfies a relationship that the second deposition speed≧the first deposition speed≧the third deposition speed.
摘要翻译：提供了在基板上沉积具有多层结构和不同沉积速度的金属氮化物膜的方法。该方法通过以第一沉积速度在基板上形成第一下部金属氮化物膜，以第二沉积速度在第一下部金属氮化物膜上形成第二下部金属氮化物膜，并形成具有通过以第三沉积速度形成第一下部金属氮化物膜和第二个下部金属氮化物膜而形成的下部TiN膜上的氮（N）含量大，以提高相对于暴露于空气/水分的稳定性。具有多层结构的金属氮化物膜的沉积速度满足第二沉积速度> =第一沉积速度> =第三沉积速度的关系。

5. 发明授权

US06261911B1 Method of manufacturing a junction in a semiconductor device 有权
标题翻译：在半导体器件中制造结的方法
公开(公告)号：US06261911B1
公开(公告)日：2001-07-17
申请号：US09502782
申请日：2000-02-11
申请人： Jung Ho Lee , Seung Chul Lee , Noh Yeal Kwak , In Seok Yeo , Sahng Kyoo Lee
发明人： Jung Ho Lee , Seung Chul Lee , Noh Yeal Kwak , In Seok Yeo , Sahng Kyoo Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66628
摘要： The present invention relates to a method of manufacturing a junction in a semiconductor device. When forming an elevated source/drain junction (ESD) of a buried channel field effect transistor (BC-FET) using a selective epitaxial growth (SEG) technique, a self-aligned epitaxial silicon (SESS) is formed on the lower portion of a gate side-wall spacer, resulting in the improvement of a short channel characteristic by suppressing a facet occurred when forming an elevated source/drain junction (EDS) of the buried channel field effect transistors (BC-FETs) using a selective epitaxial growth (SEG) technique as well as the increase of the current density by lowering the series resistance of source/drain extension.
摘要翻译：本发明涉及在半导体器件中制造结的方法。当使用选择性外延生长（SEG）技术形成掩埋沟道场效应晶体管（BC-FET）的升高的源极/漏极结（ESD）时，自对准外延硅（SESS）形成在通过使用选择性外延生长（SEG）形成掩埋沟道场效应晶体管（BC-FET）形成升高的源极/漏极结（EDS）时发生的小面，导致短沟道特性的改善，）技术，以及通过降低源极/漏极延伸的串联电阻来增加电流密度。

6. 发明授权

US5880039A Method for forming interlayer insulating film of a semiconductor device 失效
标题翻译：用于形成半导体器件的层间绝缘膜的方法
公开(公告)号：US5880039A
公开(公告)日：1999-03-09
申请号：US847256
申请日：1997-05-01
申请人： Sahng Kyoo Lee
发明人： Sahng Kyoo Lee
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/02
CPC分类号： H01L21/02129 , H01L21/02112 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31053 , H01L21/31612 , H01L21/76819
摘要： A method for forming an interlayer insulating film of semiconductor device is disclosed. A first interlayer insulating film is deposited on the entire top surface of a semiconductor device comprising a high step cell area and lower step periphery area, followed by the thermal treatment thereof. A second interlayer insulating film which is more resistant to etch than the first interlayer insulating film is deposited. Again, a third interlayer insulating film is deposited over the second interlayer insulating film, followed by the heat treatment thereof. These interlayer insulating films are planarized by a CMP process. Upon the CMP process, the first interlayer insulating film is rapidly etched out while the second interlayer insulating film is slowly removed and this difference in etching rate allows the polishing end point to be readily detected without an additional detector. Thus, the lower step periphery area can be prevented from being over-polished, so that a wholly planar structure free of the dishing problem can be obtained, thus facilitating the subsequent processes.
摘要翻译：公开了一种用于形成半导体器件的层间绝缘膜的方法。第一层间绝缘膜沉积在半导体器件的整个顶表面上，该半导体器件包括高阶段电池区域和较低的台阶周边面积，随后进行热处理。沉积比第一层间绝缘膜更耐蚀刻的第二层间绝缘膜。再次，在第二层间绝缘膜上沉积第三层间绝缘膜，然后进行热处理。这些层间绝缘膜通过CMP工艺平坦化。在CMP工艺中，第一层间绝缘膜被快速蚀刻出来，同时缓慢地除去第二层间绝缘膜，并且蚀刻速率的差异允许在没有另外的检测器的情况下容易地检测抛光终点。因此，可以防止下阶梯周边区域被过度抛光，从而可以获得没有凹陷问题的整体平面结构，从而有助于后续工艺。

7. 发明授权

US5953622A Method for fabricating semiconductor wafers 失效
标题翻译：制造半导体晶圆的方法
公开(公告)号：US5953622A
公开(公告)日：1999-09-14
申请号：US929793
申请日：1997-09-15
申请人： Sahng Kyoo Lee , Sang Kyun Park
发明人： Sahng Kyoo Lee , Sang Kyun Park
IPC分类号： H01L21/265 , H01L21/02 , H01L21/20 , H01L21/762 , H01L27/12 , H01L21/76
CPC分类号： H01L21/2007 , H01L21/76254
摘要： A method for fabricating silicon-on-insulator (SOI) wafers which is capable of simplifying the fabrication process while improving the productivity of SOI wafers. In accordance with this method, a first wafer formed with a thermal oxide film is bonded to a second wafer formed with an oxygen ion-implanted region and a hydrogen ion-implanted region. The bonded wafer structure is annealed and then cut along the hydrogen ion-implanted region, so that it is divided into two wafer structures. The wafer structure including the first wafer is annealed to obtain a strengthened chemical coupling property. The wafer structure including the second wafer is annealed to oxidize the oxygen ion-implanted region of the second wafer, thereby forming an oxide film in the second wafer. The first and second wafers are then planarized, thereby forming a pair of SOI wafers.
摘要翻译：一种制造绝缘体上硅（SOI）晶片的方法，其能够简化制造工艺，同时提高SOI晶片的生产率。根据该方法，形成有热氧化膜的第一晶片与形成有氧离子注入区域和氢离子注入区域的第二晶片接合。接合晶片结构退火，然后沿着氢离子注入区切割，从而将其分成两个晶片结构。包括第一晶片的晶片结构被退火以获得增强的化学耦合性能。包括第二晶片的晶片结构被退火以氧化第二晶片的氧离子注入区域，从而在第二晶片中形成氧化物膜。然后将第一和第二晶片平坦化，从而形成一对SOI晶片。

8. 发明授权

US5707686A Method for preventing moisture from being absorbed into impurity-contained insulating layer 失效
标题翻译：防止水分吸收到含杂质的绝缘层中的方法
公开(公告)号：US5707686A
公开(公告)日：1998-01-13
申请号：US558585
申请日：1995-10-31
申请人： Sahng Kyoo Lee
发明人： Sahng Kyoo Lee
IPC分类号： B05D5/00 , H01L21/3105 , H01L23/532 , B05D3/12
CPC分类号： H01L21/3105 , B05D5/00 , H01L23/5329 , H01L2924/0002 , Y10S438/976
摘要： A method for preventing moisture from being absorbed into an impurity-contained insulating layer is disclosed, including the steps of: forming an impurity-contained insulating layer on a substrate; and coating a material of an alcohol group on the impurity-contained insulating layer, to form an alcohol film.
摘要翻译：公开了一种防止水分吸收到含杂质的绝缘层中的方法，包括以下步骤：在衬底上形成含杂质的绝缘层; 并在杂质含有绝缘层上涂覆醇基的材料，形成醇膜。

9. 发明授权

US06255206B1 Method of forming gate electrode with titanium polycide structure 有权
标题翻译：用聚硅氧烷结构形成栅电极的方法
公开(公告)号：US06255206B1
公开(公告)日：2001-07-03
申请号：US09434647
申请日：1999-11-05
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L21/31683
摘要： A method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, is disclosed. According to the present invention, a gate oxide layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer and the titanium silicide layer and the polysilicon layer are etched using the mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using re-oxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation. Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C. and the oxide layer is formed to the thickness of 30 to 60 Å, preferably, about 50 Å.
摘要翻译：公开了一种形成具有可以防止栅电极的异常氧化并降低栅电极的电阻率的多晶硅化钛结构的栅电极的方法。根据本发明，栅极氧化物层在半导体衬底上依次形成多晶硅层和硅化钛层。然后在硅化钛层上形成栅极形状的掩模绝缘层，并且使用掩模绝缘层蚀刻钛硅化物层和多晶硅层以形成栅电极。此后，使用再氧化工艺氧化基板，在栅电极的侧壁和基板的表面上形成均匀厚度的氧化物层。这里，使用干式氧化在750℃以下的温度下进行再氧化处理。此外，再次氧化处理在700-750℃的温度下进行，氧化物层的厚度形成为30至60埃，优选为约50埃。

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