专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06262464B1 Encapsulated MEMS brand-pass filter for integrated circuits 失效
标题翻译：用于集成电路的封装的MEMS品牌滤波器
公开(公告)号：US06262464B1
公开(公告)日：2001-07-17
申请号：US09596725
申请日：2000-06-19
申请人： Kevin K. Chan , Christopher Jhanes , Leathen Shi , James L. Speidell , James F. Ziegler
发明人： Kevin K. Chan , Christopher Jhanes , Leathen Shi , James L. Speidell , James F. Ziegler
IPC分类号： H01L2714
CPC分类号： H03H3/0072 , H03H9/1057 , H03H9/2463 , H03H9/465
摘要： Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electro-mechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.
摘要翻译：使用封装的微机电系统（MEMS）装置的通信信号混合和滤波系统和方法。此外，公开了一种制造简单的，单一构造的微机电系统（MEMS）装置的方法，该微机电系统（MEMS）装置结合了信号混合和滤波的步骤，并且其结构和操作比目前的装置更小，更便宜和更可靠在技术上受雇。

2. 发明授权

US06399406B2 Encapsulated MEMS band-pass filter for integrated circuits and method of fabrication thereof 失效
标题翻译：用于集成电路的封装的MEMS带通滤波器及其制造方法
公开(公告)号：US06399406B2
公开(公告)日：2002-06-04
申请号：US09840264
申请日：2001-04-23
申请人： Kevin K. Chan , Christopher Jhanes , Leathen Shi , James L. Speidell , James F. Ziegler
发明人： Kevin K. Chan , Christopher Jhanes , Leathen Shi , James L. Speidell , James F. Ziegler
IPC分类号： H01L2100
CPC分类号： H03H3/0072 , H03H9/1057 , H03H9/2463 , H03H9/465
摘要： Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electromechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.
摘要翻译：使用封装的微机电系统（MEMS）装置的通信信号混合和滤波系统和方法。此外，公开了一种制造简单，单一构造的微机电系统（MEMS）装置的方法，其组合了信号混合和滤波的步骤，并且其结构和操作更小，更便宜和更可靠，与目前在技术。

3. 发明授权

US07485518B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US07485518B2
公开(公告)日：2009-02-03
申请号：US11684855
申请日：2007-03-12
申请人： Kevin K. Chan , Jack Q Chan , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack Q Chan , Kern Rim , Leathen Shi
IPC分类号： H01L21/336
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

4. 发明授权

US08017499B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 有权
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US08017499B2
公开(公告)日：2011-09-13
申请号：US12125175
申请日：2008-05-22
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L21/336
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

5. 发明授权

US07566631B2 Low temperature fusion bonding with high surface energy using a wet chemical treatment 失效
标题翻译：使用湿化学处理的低表面能低温熔接
公开(公告)号：US07566631B2
公开(公告)日：2009-07-28
申请号：US11411395
申请日：2006-04-26
申请人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
发明人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra, Jr. , Leathen Shi , Dinkar V. Singh
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够在低温（小于或等于400℃）下将诸如半导体（例如Si）的两个晶片极度直接结合到绝缘体（例如SiO 2）。使用这些表面处理中的一些已经实现了接合界面的高达〜4835±675mJ / m 2的表面能。该值与显着更高的处理温度（小于1000℃）报告的值相当。这里也可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙结合界面。

6. 发明申请

US20080254594A1 STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS 失效
标题翻译：应变硅CMOS混合晶体取向
公开(公告)号：US20080254594A1
公开(公告)日：2008-10-16
申请号：US12143912
申请日：2008-06-23
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/30
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

7. 发明授权

US07217949B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
标题翻译：拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）
公开(公告)号：US07217949B2
公开(公告)日：2007-05-15
申请号：US10883443
申请日：2004-07-01
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L29/06
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.
摘要翻译：提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

8. 发明申请

US20080227270A1 LOW TEMPERATURE FUSION BONDING WITH HIGH SURFACE ENERGY USING A WET CHEMICAL TREATMENT 失效
标题翻译：使用湿式化学处理的高温表面能量的低温熔融粘结
公开(公告)号：US20080227270A1
公开(公告)日：2008-09-18
申请号：US12128259
申请日：2008-05-28
申请人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra , Leathen Shi , Dinkar V. Singh
发明人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra , Leathen Shi , Dinkar V. Singh
IPC分类号： H01L21/46
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够使诸如半导体（例如Si）的两个晶片与绝缘体（例如，SiO 2）的极强直接接合，在低温（小于或等于400℃）。使用这些表面处理中的一些已经实现了键合界面的高达〜4835±675mJ / m 2的表面能。该值与报告的显着更高的处理温度（小于1000℃）的值相当。本文还可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙键合界面。

9. 发明申请

US20080220588A1 STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI) 有权
公开(公告)号：US20080220588A1
公开(公告)日：2008-09-11
申请号：US12125175
申请日：2008-05-22
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L21/46
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

10. 发明授权

US06660598B2 Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region 失效
标题翻译：形成具有稀疏沟道区的完全耗尽的SOI（绝缘体上硅）MOSFET的方法
公开(公告)号：US06660598B2
公开(公告)日：2003-12-09
申请号：US10084550
申请日：2002-02-26
申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
发明人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78612
摘要： A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.
摘要翻译：提供了具有低源极和漏极电阻以及最小重叠电容的0.05微米通道长度的全耗尽SOI MOSFET器件及其制造方法。根据本发明的方法，首先在SOI层顶部形成至少一个虚拟栅极区域。虚拟栅极区域至少包括牺牲多晶硅区域和位于牺牲多晶硅区域的侧壁上的第一氮化物间隔物。接下来，形成与伪栅极区的上表面共面的氧化物层，然后除去牺牲多晶硅区域，以露出SOI层的一部分。在SOI层的暴露部分中形成一个变薄的器件沟道区，此后在第一氮化物间隔物的暴露的壁上形成内部氮化物间隔物。接下来，在减薄的器件沟道区上形成栅极区，然后除去氧化物层，以便暴露出SOI层的比较器件沟道区更厚的部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式