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1. 发明授权

US08053819B2 Three-dimensional cascaded power distribution in a semiconductor device 有权
标题翻译：半导体器件中的三维级联功率分布
公开(公告)号：US08053819B2
公开(公告)日：2011-11-08
申请号：US12120899
申请日：2008-05-15
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

2. 发明申请

US20080023731A1 Three-dimensional cascaded power distribution in a semiconductor device 有权
标题翻译：半导体器件中的三维级联功率分布
公开(公告)号：US20080023731A1
公开(公告)日：2008-01-31
申请号：US11496120
申请日：2006-07-31
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

3. 发明申请

US20080203445A1 Three-Dimensional Cascaded Power Distribution in a Semiconductor Device 有权
标题翻译：半导体器件中的三维级联配电
公开(公告)号：US20080203445A1
公开(公告)日：2008-08-28
申请号：US12120899
申请日：2008-05-15
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.
摘要翻译：具有降低的功率损耗和/或噪声的IC结构包括以基本上垂直的尺寸堆叠的两个或更多个有源半导体区域，每个有源半导体区域包括有源层。 IC结构还包括两个或更多个电压供应平面，每个电压供应平面对应于相应的一个有源层。

4. 发明授权

US07402854B2 Three-dimensional cascaded power distribution in a semiconductor device 有权
公开(公告)号：US07402854B2
公开(公告)日：2008-07-22
申请号：US11496120
申请日：2006-07-31
申请人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
发明人： Kerry Bernstein , Paul W. Coteus , Philip George Emma , Allan Mark Hartstein , Stephen V. Kosonocky , Ruchir Puri , Mark B. Ritter
IPC分类号： H01L29/80
CPC分类号： G11C5/063 , G11C5/14 , H01L21/8221 , H01L27/0688 , H03H1/0007
摘要： An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

5. 发明申请

US20080165521A1 THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS 审中-公开
标题翻译：用于自检和自修复集成电路的三维架构
公开(公告)号：US20080165521A1
公开(公告)日：2008-07-10
申请号：US11621188
申请日：2007-01-09
申请人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
发明人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
IPC分类号： H05K7/00 , H01L21/50
CPC分类号： H01L24/83 , H01L21/6835 , H01L21/8221 , H01L24/26 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L2221/68354 , H01L2224/8385 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/07802 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.
摘要翻译：三维结构芯片包括基本芯片，其包括集成在其上并被配置为执行电信号操作的单元。从基层分开制造有源层。有源层包括用于服务于基片的单元的部件。有源层被结合到基片，使得该元件在该单元的垂直方向上对准。电连接通过基底芯片和有源层中的至少一个的垂直层将单元连接到部件。

6. 发明授权

US07913202B2 Wafer level I/O test, repair and/or customization enabled by I/O layer 有权
标题翻译：通过I / O层启用晶圆级I / O测试，修复和/或定制
公开(公告)号：US07913202B2
公开(公告)日：2011-03-22
申请号：US11945308
申请日：2007-11-27
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G06F17/50
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

7. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

8. 发明申请

US20080068039A1 Wafer Level I/O Test, Repair and/or Customization Enabled by I/O layer 有权
标题翻译：由I / O层启用的晶片级I / O测试，修复和/或定制
公开(公告)号：US20080068039A1
公开(公告)日：2008-03-20
申请号：US11945308
申请日：2007-11-27
申请人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
IPC分类号： H03K19/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

9. 发明申请

US20070081410A1 WAFER LEVEL I/O TEST AND REPAIR ENABLED BY I/O LAYER 失效
标题翻译：由I / O层启用的WAFER LEVEL I / O测试和维修
公开(公告)号：US20070081410A1
公开(公告)日：2007-04-12
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark Ritter , Jeannine Trewhella , Albert Young
IPC分类号： G11C8/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

10. 发明授权

US08756541B2 Relative ordering circuit synthesis 有权
标题翻译：相对排序电路综合
公开(公告)号：US08756541B2
公开(公告)日：2014-06-17
申请号：US13431368
申请日：2012-03-27
申请人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
发明人： Minsik Cho , Ruchir Puri , Haoxing Ren , Xiaoping Tang , Hua Xiang , Matthew Mantell Ziegler
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.
摘要翻译：本文提供了相对排序电路合成的系统和方法。一个方面提供了通过计算设备可访问的至少一个处理器生成至少一个电路设计; 其中产生至少一个电路设计包括：基于至少一个电路设计布局生成至少一个相对顺序结构，所述至少一个相对顺序结构包括与至少一个电路元件相关联的至少一个放置约束; 根据所述至少一个放置约束将与所述至少一个放置约束相关联的所述至少一个电路元件放置在电路设计内; 以及将不与所述至少一个放置约束相关联的电路元件放置在所述电路设计内。本文还描述了其它实施例和方面。

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