专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07913202B2 Wafer level I/O test, repair and/or customization enabled by I/O layer 有权
标题翻译：通过I / O层启用晶圆级I / O测试，修复和/或定制
公开(公告)号：US07913202B2
公开(公告)日：2011-03-22
申请号：US11945308
申请日：2007-11-27
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G06F17/50
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

2. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

3. 发明授权

US08495540B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 失效
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08495540B2
公开(公告)日：2013-07-23
申请号：US13449009
申请日：2012-04-17
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

4. 发明授权

US08407632B2 Detecting dose and focus variations during photolithography 失效
标题翻译：在光刻期间检测剂量和聚焦变化
公开(公告)号：US08407632B2
公开(公告)日：2013-03-26
申请号：US12881548
申请日：2010-09-14
申请人： Ibrahim M. Elfadel , Ying Liu , Stanislav Polonsky , Amith Singhee
发明人： Ibrahim M. Elfadel , Ying Liu , Stanislav Polonsky , Amith Singhee
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F7/70658
摘要： A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference.
摘要翻译：在说明性实施例中提供了用于在光刻期间检测剂量和聚焦变化的方法，系统和计算机可用程序产品。在晶片上形成测试形状，该晶片用于制造集成电路，该测试形状使用为制造预定的剂量值和聚焦值形成。测量测试形状的电容。使用提取模型将电容解析为第二计量值和第二焦点值。计算给药值和第二给药值之间的差异。基于差异，建议制造中的剂量调整。

5. 发明申请

US20120290778A1 INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
标题翻译：增加容量异质存储元素
公开(公告)号：US20120290778A1
公开(公告)日：2012-11-15
申请号：US13557294
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.
摘要翻译：提供异构存储元件中的增加的容量，包括用于在异构存储器中存储数据的方法，该方法包括接收对应于其中至少两个存储器单元支持不同数据电平的存储器单元块的写入消息和写入地址，确定物理特性并且响应于物理特性识别与存储器单元块相关联的虚拟存储器。对每个虚拟存储器执行以下操作：生成描述虚拟存储器中的虚拟单元的约束向量; 以及响应于所述约束向量和所述写入数据计算虚拟写入向量，所述计算包括按顺序将所述写入数据逐位写入到所述虚拟存储器中，跳过已知被粘附到特定值的位置，如约束向量。虚拟写入向量被组合成写入字，并将写入字输出到存储器单元块。

6. 发明授权

US08245169B2 Generating capacitance look-up tables for wiring patterns in the presence of metal fills 有权
标题翻译：在存在金属填充物的情况下为布线图生成电容查找表
公开(公告)号：US08245169B2
公开(公告)日：2012-08-14
申请号：US12648456
申请日：2009-12-29
申请人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
发明人： Ibrahim M. Elfadel , Tarek Ali El Moselhy , David J. Widiger
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072 , G06F17/5036 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H05K2201/09781
摘要： A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.
摘要翻译：计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。零电荷方程式确定驻留在所选金属填充上的总电荷等于零。计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

7. 发明申请

US20120165624A1 SIGNAL PROCESSING APPARATUS 失效
公开(公告)号：US20120165624A1
公开(公告)日：2012-06-28
申请号：US13397564
申请日：2012-02-15
申请人： Mohamed K. Diab , Esmaiel Kiani-Azarbayjany , Ibrahim M. Elfadel , Rex J. McCarthy , Walter M. Weber , Robert A. Smith
发明人： Mohamed K. Diab , Esmaiel Kiani-Azarbayjany , Ibrahim M. Elfadel , Rex J. McCarthy , Walter M. Weber , Robert A. Smith
IPC分类号： A61B5/0205 , A61B5/08 , A61B5/024 , A61B5/1455
CPC分类号： A61B5/0205 , A61B5/021 , A61B5/02154 , A61B5/024 , A61B5/029 , A61B5/0402 , A61B5/0476 , A61B5/0816 , A61B5/14532 , A61B5/14546 , A61B5/14551 , A61B5/14552 , A61B5/4821 , A61B5/7214 , A61B5/7246 , A61B5/7253 , A61B5/7257 , A61B5/726 , A61B6/00 , A61B8/00 , A61B8/5276 , G06K9/0051 , H04B1/123
摘要： The present invention involves a method and an apparatus for analyzing measured signals, including the determination of a measurement of oxygen saturation and respiration rate in the measured signals during a calculation of a physiological parameter of a monitored patient. Use of this invention is described in particular detail with respect to oximetry-based measurements but extends to other types of measurements.

8. 发明授权

US07921004B2 Methods and apparatus for analyzing transmission lines with decoupling of connectors and other circuit elements 有权
标题翻译：用于分析连接器和其他电路元件去耦的传输线的方法和装置
公开(公告)号：US07921004B2
公开(公告)日：2011-04-05
申请号：US12061269
申请日：2008-04-02
申请人： Ibrahim M. Elfadel , Hao Ming Huang , Albert E. Ruehli
发明人： Ibrahim M. Elfadel , Hao Ming Huang , Albert E. Ruehli
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and apparatus are provided for analyzing transmission lines with decoupling of connectors and other circuit elements. According to one aspect of the invention, circuits with one or more parasitic elements are analyzed by partitioning at least one of the parasitic elements in a transverse manner; identifying a plurality of subcircuits each comprised of partitioned circuit elements from the plurality of transmission lines and one or more parasitic elements in a given path; wherein each of the subcircuits is associated with a path in the circuit; performing a waveform relaxation analysis between each of the subcircuits; and repeating the step of performing the waveform relaxation analysis using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred. The circuit can optionally further comprise one or more transmission lines which would also be partitioned in a transverse manner.
摘要翻译：提供了用于分析连接器和其他电路元件去耦的传输线的方法和装置。根据本发明的一个方面，通过以横向方式分隔至少一个寄生元件来分析具有一个或多个寄生元件的电路; 识别多个子电路，每个子电路由来自所述多个传输线的分隔电路元件和给定路径中的一个或多个寄生元件组成; 其中每个子电路与电路中的路径相关联; 在每个子电路之间进行波形弛豫分析; 并且重复使用在前一次迭代中确定的波形执行波形弛豫分析的步骤，直到发生对所得波形的收敛。电路可以可选地进一步包括一个或多个也将以横向分隔的传输线。

9. 发明申请

US20110078642A1 Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine 有权
标题翻译：使用形状处理引擎计算VLSI布局中的电容梯度的方法
公开(公告)号：US20110078642A1
公开(公告)日：2011-03-31
申请号：US12570418
申请日：2009-09-30
申请人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
发明人： Ibrahim M. Elfadel , Lewis William Dewey, III , Tarek A. El-Moselhy , David J. Widiger , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Computing the gradients of capacitances in an integrated circuit chip layout with respect to design and process parameters is described. Included is a shape processing engine in the form of a variational mapping engine and a capacitance calculation engine that includes a gradient calculation engine. The variational mapping engine translates physical parameter variations into variations on the edges of the elementary patterns to which the layout of the integrated circuit is decomposed. The gradient calculation engine computes capacitance gradients by combining information from two sources. The first source consists of pre-existing gradients in a capacitance lookup table. The second source consists of analytical expressions of capacitance correction factors.
摘要翻译：描述了关于设计和工艺参数的集成电路芯片布局中的电容梯度的计算。包括变形映射引擎形式的形状处理引擎和包括梯度计算引擎的电容计算引擎。变分映射引擎将物理参数变化转换为集成电路的布局分解到的基本图案的边缘上的变化。梯度计算引擎通过组合来自两个来源的信息来计算电容梯度。第一个源包括电容查找表中预先存在的梯度。第二个来源包括电容校正因子的解析表达式。

10. 发明授权

US07376453B1 Signal processing apparatus 失效
公开(公告)号：US07376453B1
公开(公告)日：2008-05-20
申请号：US09144897
申请日：1998-09-01
申请人： Mohamed K. Diab , Esmaiel Kiani-Azarbayjany , Ibrahim M. Elfadel , Rex J. McCarthy , Walter M. Weber , Robert A. Smith
发明人： Mohamed K. Diab , Esmaiel Kiani-Azarbayjany , Ibrahim M. Elfadel , Rex J. McCarthy , Walter M. Weber , Robert A. Smith
IPC分类号： A61B5/1455
CPC分类号： A61B5/14551 , A61B5/7214 , A61B5/725 , A61B5/7253 , A61B5/7257 , A61B5/726 , G06K9/0051
摘要： The present invention involves method and apparatus for analyzing two measured signals that are modeled as containing primary and secondary portions. Coefficients relate the two signals according to a model defined in accordance with the present invention. In one embodiment, the present invention involves utilizing a transformation which evaluates a plurality of possible signal coefficients in order to find appropriate coefficients. Alternatively, the present invention involves using statistical functions or Fourier transform and windowing techniques to determine the coefficients relating to two measured signals. Use of this invention is described in particular detail with respect to blood oximetry measurements.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式