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1. 发明授权

US07913202B2 Wafer level I/O test, repair and/or customization enabled by I/O layer 有权
标题翻译：通过I / O层启用晶圆级I / O测试，修复和/或定制
公开(公告)号：US07913202B2
公开(公告)日：2011-03-22
申请号：US11945308
申请日：2007-11-27
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G06F17/50
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：一种用于3D芯片的设计结构，其具有通过垂直总线连接到其它3D芯片层的至少一个I / O层，使得I / O层可适应保护和片外器件驱动电路，定制电路，平移电路，转换电路和/或能够进行全面芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

2. 发明授权

US07521950B2 Wafer level I/O test and repair enabled by I/O layer 失效
标题翻译：通过I / O层启用晶圆级I / O测试和修复
公开(公告)号：US07521950B2
公开(公告)日：2009-04-21
申请号：US11163167
申请日：2005-10-07
申请人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
发明人： Kerry Bernstein , Paul Coteus , Ibrahim M. Elfadel , Philip Emma , Daniel J. Friedman , Ruchir Puri , Mark B. Ritter , Jeannine Trewhella , Albert M. Young
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28 , G01R31/00 , G01N37/00 , G06F13/20 , G06F13/36 , G06F11/00
CPC分类号： G11C29/006 , G11C29/12 , G11C29/1201 , G11C2029/1206
摘要： A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
摘要翻译：具有至少一个I / O层的3D芯片，其通过垂直总线连接到其他3D芯片层，使得所述I / O层可适应保护和芯片外设备驱动电路，定制电路，平移电路，转换电路和/或能够进行全面的芯片或晶片级测试的内置自检电路，其中I / O层用作测试头。 I / O电路或结构的替代可以使用响应于这种测试的电子熔断器等进行。

3. 发明申请

US20080165521A1 THREE-DIMENSIONAL ARCHITECTURE FOR SELF-CHECKING AND SELF-REPAIRING INTEGRATED CIRCUITS 审中-公开
标题翻译：用于自检和自修复集成电路的三维架构
公开(公告)号：US20080165521A1
公开(公告)日：2008-07-10
申请号：US11621188
申请日：2007-01-09
申请人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
发明人： KERRY BERNSTEIN , Paul William Coteus , Ibrahim (Abe) M. Elfadel , Philip George Emma , Kathryn W. Guarini , Thomas Fleischman , Allan Mark Hartstein , Ruchir Puri , Mark B. Ritter , Jeannine Madelyn Trewhella , Albert M. Young
IPC分类号： H05K7/00 , H01L21/50
CPC分类号： H01L24/83 , H01L21/6835 , H01L21/8221 , H01L24/26 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L2221/68354 , H01L2224/8385 , H01L2225/06524 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/07802 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043
摘要： A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.
摘要翻译：三维结构芯片包括基本芯片，其包括集成在其上并被配置为执行电信号操作的单元。从基层分开制造有源层。有源层包括用于服务于基片的单元的部件。有源层被结合到基片，使得该元件在该单元的垂直方向上对准。电连接通过基底芯片和有源层中的至少一个的垂直层将单元连接到部件。

4. 发明授权

US08962448B2 Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier 有权
标题翻译：用用于制造使用界面晶片作为永久载体的3D集成电路器件的程序编码的计算机可读介质
公开(公告)号：US08962448B2
公开(公告)日：2015-02-24
申请号：US13572004
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/46
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译：提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

5. 发明授权

US07947509B2 Optoelectronic detection system 有权
标题翻译：光电检测系统
公开(公告)号：US07947509B2
公开(公告)日：2011-05-24
申请号：US11800607
申请日：2007-05-07
申请人： James Douglas Harper , Richard Hart Mathews , Bernadette Johnson , Martha Susan Petrovick , Ann Rundell , Frances Ellen Nargi , Timothy Stephens , Linda Marie Mendenhall , Mark Alexander Hollis , Albert M. Young , Todd H. Rider , Eric David Schwoebel , Trina Rae Vian
发明人： James Douglas Harper , Richard Hart Mathews , Bernadette Johnson , Martha Susan Petrovick , Ann Rundell , Frances Ellen Nargi , Timothy Stephens , Linda Marie Mendenhall , Mark Alexander Hollis , Albert M. Young , Todd H. Rider , Eric David Schwoebel , Trina Rae Vian
IPC分类号： G01N21/00 , G01N21/01 , G01N21/62 , G01N21/63 , G01N21/64 , G01N33/52
CPC分类号： G01N33/554 , G01N15/0205 , G01N21/07 , G01N21/64 , G01N21/6428 , G01N21/75 , G01N21/76 , G01N33/54373 , G01N33/54393 , G01N33/56983 , G01N33/582 , G01N2021/6439 , G01N2201/025 , G01N2201/061 , Y10S435/808 , Y10S436/805
摘要： The invention relates to optoelectronic systems for detecting one or more target particles. The system includes a reaction chamber, a specimen collector, an optical detector, and a reservoir containing cells, each of the cells having receptors which are present on the surface of each cell and are specific for the target particle to be detected, where binding of the target particle to the receptors directly or indirectly activates a reporter molecule, thereby producing a measurable optical signal.
摘要翻译：本发明涉及用于检测一个或多个目标颗粒的光电子系统。该系统包括反应室，样品收集器，光学检测器和含有细胞的储存器，每个细胞具有存在于每个细胞表面上并且对待检测的靶颗粒是特异性的受体，其中结合受体的目标颗粒直接或间接激活报告分子，从而产生可测量的光信号。

6. 发明申请

US20100270676A1 ADAPTIVE INTERCONNECT STRUCTURE 失效
标题翻译：自适应互连结构
公开(公告)号：US20100270676A1
公开(公告)日：2010-10-28
申请号：US12430416
申请日：2009-04-27
申请人： Leland Chang , Matthew R. Wordeman , Albert M. Young
发明人： Leland Chang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L25/0657 , H01L23/5252 , H01L23/5256 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
摘要翻译：半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。一个接触垫可以设置有多个可编程触点。在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

7. 发明授权

US07652278B2 Programmable via structure and method of fabricating same 有权
标题翻译：可编程通孔结构及其制造方法
公开(公告)号：US07652278B2
公开(公告)日：2010-01-26
申请号：US11612631
申请日：2006-12-19
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Chung H. Lam , Albert M. Young
IPC分类号： H01L29/02 , H01L21/06
CPC分类号： H01L45/122 , H01L45/06 , H01L45/1206 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A programmable via structure is provided as well as a method of fabricating the same. The inventive programmable via a semiconductor substrate. An oxide layer such as a thermal oxide is located on a surface of the semiconductor substrate. A patterned heating material is located on a surface of the oxide layer. The inventive structure also includes a patterned dielectric material having a least one via filled with a phase change material (PCM). The patterned dielectric material including the PCM filled via is located on a surface of the patterned heating material. A patterned diffusion barrier is located on an exposed surface of said at least one via filled with the phase change material. The inventive structure also includes contact vias that extend through the patterned dielectric material. The contact vias are filled with a conductive material which also extends onto the upper surface of the patterned dielectric material. A conductive material which serves as the input of the device is located atop the patterned diffusion barrier that is located directly above the via that is filled with the phase change material.
摘要翻译：提供了可编程通孔结构以及其制造方法。本发明可编程通过半导体衬底。诸如热氧化物的氧化物层位于半导体衬底的表面上。图案化的加热材料位于氧化物层的表面上。本发明的结构还包括具有填充有相变材料（PCM）的至少一个通孔的图案化电介质材料。包括PCM填充通孔的图案化电介质材料位于图案化加热材料的表面上。图案化扩散阻挡层位于所述至少一个充满相变材料的通孔的暴露表面上。本发明的结构还包括延伸通过图案化电介质材料的接触孔。接触通孔填充有也延伸到图案化电介质材料的上表面上的导电材料。用作器件输入的导电材料位于图案化的扩散阻挡层的顶部，其位于通过相变材料填充的正上方。

8. 发明授权

US07129783B2 Hybrid active combiner and circulator 有权
公开(公告)号：US07129783B2
公开(公告)日：2006-10-31
申请号：US10973361
申请日：2004-10-25
申请人： Albert M. Young , Samuel S. Osofsky , Keven S. MacGowan , David A. Ksienski
发明人： Albert M. Young , Samuel S. Osofsky , Keven S. MacGowan , David A. Ksienski
IPC分类号： H03F3/60
CPC分类号： H03F1/523 , H03F3/191 , H03F3/604 , H03F2200/192 , H03F2200/198 , H03F2200/204 , H03F2200/294 , H03F2200/372
摘要： The hybrid active combiner and circulators serves as a coupler and is a three port network that integrates a directional coupler topology with active devices placed in the coupling paths in order to synthesize a low-loss active combiner circuit or a circulator device with minimal insertion losses. The coupler can have multiple stage amplifiers with transconductance values set according the Pascal's triangle for improved performance, and can function as a low cost and low weight transceiver well suited for various communications systems.

9. 发明授权

US09005989B2 Optoelectronic detection system 有权
标题翻译：光电检测系统
公开(公告)号：US09005989B2
公开(公告)日：2015-04-14
申请号：US13039780
申请日：2011-03-03
申请人： James Douglas Harper , Richard Hart Mathews , Bernadette Johnson , Martha Susan Petrovick , Ann Rundell , Frances Ellen Nargi , Timothy Stephens , Linda Marie Mendenhall , Mark Alexander Hollis , Albert M. Young , Todd H. Rider , Eric David Schwoebel , Trina Rae Vian
发明人： James Douglas Harper , Richard Hart Mathews , Bernadette Johnson , Martha Susan Petrovick , Ann Rundell , Frances Ellen Nargi , Timothy Stephens , Linda Marie Mendenhall , Mark Alexander Hollis , Albert M. Young , Todd H. Rider , Eric David Schwoebel , Trina Rae Vian
IPC分类号： G01N21/76 , G01N33/58 , G01N33/543 , G01N21/07 , G01N21/64
CPC分类号： G01N33/554 , G01N15/0205 , G01N21/07 , G01N21/64 , G01N21/6428 , G01N21/75 , G01N21/76 , G01N33/54373 , G01N33/54393 , G01N33/56983 , G01N33/582 , G01N2021/6439 , G01N2201/025 , G01N2201/061 , Y10S435/808 , Y10S436/805
摘要： The invention relates to optoelectronic systems for detecting one or more target particles. The system includes a reaction chamber, a specimen collector, an optical detector, and a reservoir containing cells, each of the cells having receptors which are present on the surface of each cell and are specific for the target particle to be detected, where binding of the target particle to the receptors directly or indirectly activates a reporter molecule, thereby producing a measurable optical signal.
摘要翻译：本发明涉及用于检测一个或多个目标颗粒的光电子系统。该系统包括反应室，样品收集器，光学检测器和含有细胞的储存器，每个细胞具有存在于每个细胞表面上并且对待检测的靶颗粒是特异性的受体，其中结合受体的目标颗粒直接或间接激活报告分子，从而产生可测量的光信号。

10. 发明授权

US08298914B2 3D integrated circuit device fabrication using interface wafer as permanent carrier 有权
标题翻译：使用接口晶片作为永久载体的3D集成电路器件制造
公开(公告)号：US08298914B2
公开(公告)日：2012-10-30
申请号：US12194198
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/4763
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。还提供了一种用包括用于执行这种方法的指令的程序编码的有形计算机可读介质。

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