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1. 发明申请

US20070123042A1 METHODS TO FORM HETEROGENEOUS SILICIDES/GERMANIDES IN CMOS TECHNOLOGY 审中-公开
标题翻译：在CMOS技术中形成异构硅氧烷/锗的方法
公开(公告)号：US20070123042A1
公开(公告)日：2007-05-31
申请号：US11164511
申请日：2005-11-28
申请人： Kern Rim , John Ellis-Monaghan , Brian Greene , William Henson , Robert Purtell , Clement Wann , Horatio Wildman
发明人： Kern Rim , John Ellis-Monaghan , Brian Greene , William Henson , Robert Purtell , Clement Wann , Horatio Wildman
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L21/84
摘要： Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different suicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second suicides or germanides are performed sequentially or in a single step.
摘要翻译：提供了制造半导体结构的方法，其包括位于半导体结构的不同区域中的异质自杀或锗化物。异质自杀或锗化物形成在半导体层，导电层或两者上。根据本发明，本发明的方法利用不同金属的顺序沉积和图案化的组合以在半导体芯片的不同区域中形成不同的自杀或锗化物。该方法包括提供具有至少第一区域和第二区域的含Si或Ge层; 在所述第一或第二区域之一上形成第一硅化物或锗化物; 并且在不包括第一硅化物或锗化锗的另一区域上形成与第一硅化物或锗化物在组成上不同的第二硅化物或锗化物，其中形成第一和第二硅化物或锗化物的步骤依次进行或单步进行。

2. 发明申请

US20060121662A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
公开(公告)号：US20060121662A1
公开(公告)日：2006-06-08
申请号：US10904884
申请日：2004-12-02
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

3. 发明申请

US20060121665A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
标题翻译：在CMOS技术中形成自对准双重杀菌剂的方法
公开(公告)号：US20060121665A1
公开(公告)日：2006-06-08
申请号：US11254934
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

4. 发明申请

US20060121664A1 Method for forming self-aligned dual salicide in CMOS technologies 失效
公开(公告)号：US20060121664A1
公开(公告)日：2006-06-08
申请号：US11254929
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

5. 发明申请

US20070249126A1 A STRUCTURE AND METHOD FOR FABRICATION OF DEEP JUNCTION SILICON-ON-INSULATOR TRANSISTORS 失效
标题翻译：一种用于制造深层结晶硅绝缘体晶体管的结构和方法
公开(公告)号：US20070249126A1
公开(公告)日：2007-10-25
申请号：US11308685
申请日：2006-04-21
申请人： Dureseti Chidambarrao , Brian Greene , John Ellis-Monaghan
发明人： Dureseti Chidambarrao , Brian Greene , John Ellis-Monaghan
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823814
摘要： A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.
摘要翻译：提供一种用于制造晶体管结构的结构和方法。该方法包括以下步骤：（a）提供包括绝缘体上半导体（“SOI”）层的衬底，该衬底通过掩埋电介质层与衬底的主体区域分离。（b）首先注入SOI层以在SOI层与掩埋介电层的界面处实现预定的掺杂剂浓度。以及（c）第二次注入所述SOI层以在多晶半导体栅极导体（“多晶硅”）中以及在与所述多晶硅栅极相邻设置的源极和漏极区域中实现预定的掺杂剂浓度，其中所述第一注入的最大深度大于第二次植入的最大深度。

6. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

7. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

8. 发明授权

US07217968B2 Recessed gate for an image sensor 有权
标题翻译：嵌入式门用于图像传感器
公开(公告)号：US07217968B2
公开(公告)日：2007-05-15
申请号：US10905097
申请日：2004-12-15
申请人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
发明人： James W. Adkisson , John Ellis-Monaghan , Mark D. Jaffe , Jerome B. Lasky
IPC分类号： H01L31/062
CPC分类号： H01L27/14603 , H01L27/14601 , H01L27/14689 , H01L29/66621
摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.
摘要翻译：一种新颖的图像传感器单元结构及其制造方法。成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区。栅极导体底部的一部分凹陷在基板的表面下方。优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

9. 发明申请

US20060286778A1 METHOD OF MANUFACTURING DUAL ORIENTATION WAFERS 失效
标题翻译：制造双取向波的方法
公开(公告)号：US20060286778A1
公开(公告)日：2006-12-21
申请号：US11160365
申请日：2005-06-21
申请人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
发明人： Brent Anderson , John Ellis-Monaghan , Alain Loiseau , Kirk Peterson
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译：公开了制造双取向晶片的方法。在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。另外的隔离结构形成在沟槽内和半导体层内的硅材料内。对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

10. 发明授权

US09543356B2 Pixel sensor cell including light shield 有权
标题翻译：像素传感器单元包括遮光罩
公开(公告)号：US09543356B2
公开(公告)日：2017-01-10
申请号：US12538194
申请日：2009-08-10
申请人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
发明人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14623 , H01L27/1464
摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.
摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽像素传感器单元。在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽遮光层。在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

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