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1. 发明授权

US07533231B1 Method and circuit for increasing the memory access speed of an enhanced synchronous memory 有权
标题翻译：用于增加增强型同步存储器的存储器存取速度的方法和电路
公开(公告)号：US07533231B1
公开(公告)日：2009-05-12
申请号：US10965602
申请日：2004-10-13
申请人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
发明人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
IPC分类号： G06F13/14
CPC分类号： G11C11/4097 , G06F12/0893 , G06F2212/3042 , G11C2207/2245
摘要： A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A number of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, before application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
摘要翻译：用于操作它的存储器和方法提供了增加的数据访问速度。在一个实现中，同步存储器或SDRAM包括具有在相应相对侧上以集合排列的存储器块的中央存储器区域。提供了许多初级感测放大器组，每组都与相应的存储块集合相关联并且位于相邻的位置。在中央存储器区域中提供行缓存，并且行解码器响应于“存储体激活”命令对行地址进行解码，并将数据从解码的行地址移动到与包含解码行的存储器块相关联的初级读出放大器组地址并进入行缓存，然后将“读”命令应用于SDRAM。列解码器响应于“读取”命令解码列地址，并根据解码的列地址从高速缓存读取数据。

2. 发明授权

US06813679B2 Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM 失效
标题翻译：提高增强型同步SDRAM存储器访问速度的方法和电路
公开(公告)号：US06813679B2
公开(公告)日：2004-11-02
申请号：US10178072
申请日：2002-06-20
申请人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
发明人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
IPC分类号： G06F1208
CPC分类号： G11C11/4097 , G06F12/0893 , G06F2212/3042 , G11C2207/2245
摘要： An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
摘要翻译：用于操作它的SDRAM和方法提供了增加的数据访问速度。 SDRAM包括具有在相应相对侧上以集合排列的存储块的中央存储器区域。提供了多个原始感测放大器组，每组都与相应的存储器组的集合相关联，并位于其附近。在中央存储器区域中提供行缓存，并且行解码器响应于“存储体激活”命令对行地址进行解码，并将数据从解码的行地址移动到与包含解码行的存储器块相关联的初级读出放大器组地址和行缓存之前，应用一个“读”命令到SDRAM。列解码器响应于“读取”命令解码列地址，并根据解码的列地址从高速缓存读取数据。

3. 发明申请

US20090122619A1 Enhanced DRAM with Embedded Registers 审中-公开
标题翻译：具有嵌入式寄存器的增强型DRAM
公开(公告)号：US20090122619A1
公开(公告)日：2009-05-14
申请号：US12116097
申请日：2008-05-06
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

4. 发明授权

US5699317A Enhanced DRAM with all reads from on-chip cache and all writers to memory array 失效
标题翻译：增强型DRAM，具有从片上缓存和所有写入器到存储器阵列的所有读取
公开(公告)号：US5699317A
公开(公告)日：1997-12-16
申请号：US319289
申请日：1994-10-06
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G11C11/409
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
摘要： An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型动态随机存取存储器（DRAM）包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以静态随机存取存储器（SRAM）速度读取高速缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

5. 发明授权

US5663915A Amplifier and method for sensing having a pre-bias or coupling step 失效
标题翻译：用于具有预偏置或耦合步骤的感测的放大器和方法
公开(公告)号：US5663915A
公开(公告)日：1997-09-02
申请号：US483279
申请日：1995-06-07
申请人： Kenneth J. Mobley
发明人： Kenneth J. Mobley
IPC分类号： H03F3/45 , G11C7/06 , H03K5/24 , G11C7/00
CPC分类号： H03K5/2481 , G11C7/062 , G11C2207/063
摘要： An improved current sensing differential amplifier which includes a separate p-channel bias stage to reduce the minimum operating voltage VCC of the circuit. The separate p-channel bias stage is also used to pre-bias a driver stage to more quickly generate differential output currents. Finally, the improved current sensing differential amplifier also includes negative feedback transistors to improve the recovery time of the circuit.
摘要翻译：一种改进的电流感测差动放大器，其包括单独的p沟道偏置级，以减小电路的最小工作电压VCC。单独的p沟道偏置级还用于预偏置驱动级，以更快地产生差分输出电流。最后，改进的电流感测差动放大器还包括负反馈晶体管，以改善电路的恢复时间。

6. 发明授权

US5327026A Self-timed bootstrap decoder 失效
标题翻译：自定义自举解码器
公开(公告)号：US5327026A
公开(公告)日：1994-07-05
申请号：US18802
申请日：1993-02-17
申请人： Kim C. Hardee , Kenneth J. Mobley
发明人： Kim C. Hardee , Kenneth J. Mobley
IPC分类号： G11C11/407 , G11C8/10 , H03K17/10
CPC分类号： G11C8/10
摘要： A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line. The self-timed bootstrap signal causes a clock generator circuit to output a clock signal that will be used to bootstrap the word line. The self-timed bootstrap signal may be generated by other row decoders. The generation of the self-timed bootstrap signal by a row decoder is responsive to any variations in that decoder, thus always providing an accurate and precise timing of the clock signal to be used for the bootstrapping.
摘要翻译：行解码器，其包括提供自定时自举信号的电路。响应于行解码器的选择而产生自定时自举信号。同时，为了引导字线，电容器件被充电。自定时自举信号使时钟发生器电路输出将用于引导字线的时钟信号。自定时自举信号可以由其他行解码器产生。由行解码器产生自定时自举信号响应于该解码器中的任何变化，因此总是提供用于自举的时钟信号的准确和精确的定时。

7. 发明申请

US20080219041A1 Processing Systems and Methods for Molecular Memory 失效
标题翻译：分子记忆的处理系统和方法
公开(公告)号：US20080219041A1
公开(公告)日：2008-09-11
申请号：US12048427
申请日：2008-03-14
申请人： Werner G. Kuhr , Ritu Shrivastava , Antonio R. Gallo , Kenneth J. Mobley , Tom DeBolske
发明人： Werner G. Kuhr , Ritu Shrivastava , Antonio R. Gallo , Kenneth J. Mobley , Tom DeBolske
IPC分类号： G11C13/00
CPC分类号： H01L51/0006 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2213/34 , H01L27/285 , H01L51/0595
摘要： Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.
摘要翻译：公开了分子存储器，即结合用于电荷存储的分子的存储器。还公开了分子记忆单元，分子存储器阵列和包括分子存储器的电子器件，以及用于制造分子存储器的处理系统和方法。还公开了使半导体器件和互连能够与分子存储器一体制造的分子存储器的制造方法。

8. 发明授权

US06538928B1 Method for reducing the width of a global data bus in a memory architecture 有权
标题翻译：降低存储体系结构中全局数据总线宽度的方法
公开(公告)号：US06538928B1
公开(公告)日：2003-03-25
申请号：US09689219
申请日：2000-10-11
申请人： Kenneth J. Mobley
发明人： Kenneth J. Mobley
IPC分类号： G11C1604
CPC分类号： G11C11/4091 , G06F12/0893 , G06F2212/3042 , G11C7/10 , G11C11/4093
摘要： A memory architecture uses shared sense amplifiers (18-23) and a centralized cache (26-29) that contains M bits. The memory architecture also includes a global bus (31) connecting the sense amplifiers and the centralized cache. The global bus includes n bits, and n
摘要翻译：存储器架构使用包含M位的共享读出放大器（18-23）和集中式高速缓存（26-29）。存储器架构还包括连接读出放大器和集中式高速缓存的全局总线（31）。全局总线包括n位，n

9. 发明授权

US06501698B1 Structure and method for hiding DRAM cycle time behind a burst access 有权
标题翻译：用于将DRAM周期时间隐藏在突发访问之后的结构和方法
公开(公告)号：US06501698B1
公开(公告)日：2002-12-31
申请号：US09703765
申请日：2000-11-01
申请人： Kenneth J. Mobley
发明人： Kenneth J. Mobley
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1006 , G11C7/1018
摘要： A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.
摘要翻译：一种用于将DRAM周期时间隐藏在突发读写访问之后的方法和系统。组合的读和写数据传输区域与一组读出放大器交互以加速读和写周期。通过独立地隔离读取的数据传输区域和写入数据传输区域，可以将数据从DRAM阵列传输（1）到读取的数据传输区域，（2）从写入数据传送区域传输到DRAM阵列，并且（3 ）从写数据传输区到读数据传输区。

10. 发明授权

US5991851A Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control 失效
标题翻译：利用与相关联的SRAM缓存和内部刷新控制集成的DRAM存储器阵列的增强型信号处理随机存取存储器件
公开(公告)号：US5991851A
公开(公告)日：1999-11-23
申请号：US850802
申请日：1997-05-02
申请人： Michael Alwais , Kenneth J. Mobley
发明人： Michael Alwais , Kenneth J. Mobley
IPC分类号： G11C11/41 , G11C11/401 , G11C11/406 , G06F12/00
CPC分类号： G11C11/406
摘要： An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.
摘要翻译：利用与SRAM缓存集成的高密度DRAM内存存储器阵列和内部刷新控制功能的增强型数字信号处理随机存取存储器件，其可以在与工业标准SRAM存储器器件引脚兼容的集成电路封装中提供。存储器件提供了具有与SRAM存储器件相当性能的DSP处理器特别实用的高速存储器访问设备，但是需要显着小的管芯尺寸，这允许每个管芯区域提供更大的有效存储器容量。该设备的内部刷新功能提供了DRAM存储器阵列的所有刷新操作，以便对设备用户透明地发生，并且提供在执行刷新操作时提示相关控制器的控制信号。

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