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1. 发明授权

US5991851A Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control 失效
标题翻译：利用与相关联的SRAM缓存和内部刷新控制集成的DRAM存储器阵列的增强型信号处理随机存取存储器件
公开(公告)号：US5991851A
公开(公告)日：1999-11-23
申请号：US850802
申请日：1997-05-02
申请人： Michael Alwais , Kenneth J. Mobley
发明人： Michael Alwais , Kenneth J. Mobley
IPC分类号： G11C11/41 , G11C11/401 , G11C11/406 , G06F12/00
CPC分类号： G11C11/406
摘要： An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.
摘要翻译：利用与SRAM缓存集成的高密度DRAM内存存储器阵列和内部刷新控制功能的增强型数字信号处理随机存取存储器件，其可以在与工业标准SRAM存储器器件引脚兼容的集成电路封装中提供。存储器件提供了具有与SRAM存储器件相当性能的DSP处理器特别实用的高速存储器访问设备，但是需要显着小的管芯尺寸，这允许每个管芯区域提供更大的有效存储器容量。该设备的内部刷新功能提供了DRAM存储器阵列的所有刷新操作，以便对设备用户透明地发生，并且提供在执行刷新操作时提示相关控制器的控制信号。

2. 发明授权

US06661696B2 Ferroelectric random access memory configurable output driver circuit 有权
公开(公告)号：US06661696B2
公开(公告)日：2003-12-09
申请号：US10233276
申请日：2002-08-28
申请人： Kurt Schwartz , Michael Alwais
发明人： Kurt Schwartz , Michael Alwais
IPC分类号： G11C1122
CPC分类号： G11C7/1051 , G11C11/22
摘要： A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.

3. 发明授权

US06362675B1 Nonvolatile octal latch and D-type register 有权
标题翻译：非易失性八进制锁存器和D型寄存器
公开(公告)号：US06362675B1
公开(公告)日：2002-03-26
申请号：US09614157
申请日：2000-07-11
申请人： Michael Alwais
发明人： Michael Alwais
IPC分类号： H03K312
CPC分类号： G11C14/00
摘要： An octal transparent latch or D-type register (or flip-flop) integrated circuit device may be packaged in an industry standard logic pin-out and configuration but having nonvolatile properties such as automatically recording the output state in nonvolatile form and restoring it on power up. The nonvolatile memory elements are ideally ferroelectric capacitors, using well known ferroelectric materials such as PZT, SBT, or BST or other ferroelectric materials. EEPROM, Flash, SNOS, or other writeable nonvolatile technologies can also be used. In a particular embodiment disclosed herein, the nonvolatile elements of the integrated circuit device are written only when the latched state changes to reduce write endurance changes thereto and data changes on either the input or output data lines that are not latched have no effect.
摘要翻译：八进制透明锁存器或D型寄存器（或触发器）集成电路器件可以封装在工业标准逻辑引脚和配置中，但具有非易失性特性，例如以非易失性形式自动记录输出状态并将其恢复电力向上。非易失性存储元件理想地是使用公知的铁电材料如PZT，SBT或BST或其它铁电材料的铁电电容器。还可以使用EEPROM，闪存，SNOS或其它可写入的非易失性技术。在本文公开的特定实施例中，集成电路器件的非易失性元件仅在锁存状态改变时才被写入，以减少对其的写入耐久性改变，并且在未锁存的输入或输出数据线上的数据改变没有效果。

4. 发明授权

US06445608B1 Ferroelectric random access memory configurable output driver circuit 有权
标题翻译：铁电随机存取存储器可配置输出驱动电路
公开(公告)号：US06445608B1
公开(公告)日：2002-09-03
申请号：US09950560
申请日：2001-09-10
申请人： Kurt Schwartz , Michael Alwais
发明人： Kurt Schwartz , Michael Alwais
IPC分类号： G11C1122
CPC分类号： G11C7/1051 , G11C11/22
摘要： A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.
摘要翻译： FRAM可配置输出驱动器电路允许用户配置输出驱动器，用于CMOS电平推/拉操作或真开漏工作。该配置存储在包括FRAM单元和标准逻辑锁存器的非易失性存储器中。配置数据在上电时恢复到锁存器。用户可以随时更改配置。配置的任何更改都存储在非易失性存储器中。

5. 发明授权

US06249841B1 Integrated circuit memory device and method incorporating flash and ferroelectric random access memory arrays 失效
标题翻译：集成电路存储器件和并入闪存和铁电随机存取存储器阵列的方法
公开(公告)号：US06249841B1
公开(公告)日：2001-06-19
申请号：US09205538
申请日：1998-12-03
申请人： L. David Sikes , Michael Alwais , Donald G. Carrigan
发明人： L. David Sikes , Michael Alwais , Donald G. Carrigan
IPC分类号： G11C1112
CPC分类号： G11C11/22 , G11C11/005
摘要： An integrated circuit memory device and method incorporating Flash and ferroelectric random access memory arrays integrated on a common substrate. The present invention allows a relatively small amount of ferroelectric random access memory to mitigate many of the erase and write time disadvantages exhibited by current Flash technology devices. In particular, whether combined together as a single stand-alone memory device or embedded together as a portion of a processor, microcontroller or application specific integrated circuit (“ASIC”), a block of ferroelectric memory that is sized to match the largest sector of Flash memory can effectively compensate for the latter's slow erasure and write times.
摘要翻译：一种集成电路存储器件和方法，其集成在公共衬底上的闪存和铁电随机存取存储器阵列。本发明允许相对较少量的铁电随机存取存储器来减轻当前闪存技术设备所呈现的许多擦除和写入时间缺点。特别地，无论是作为单独的独立存储器件一起组合还是作为处理器，微控制器或专用集成电路（“ASIC”）的一部分嵌入在一起，一块铁电存储器的块，其大小适于匹配最大扇区闪存可以有效地补偿后者的缓慢擦除和写入时间。

6. 发明授权

US5963481A Embedded enhanced DRAM, and associated method 失效
标题翻译：嵌入式增强型DRAM及相关方法
公开(公告)号：US5963481A
公开(公告)日：1999-10-05
申请号：US108089
申请日：1998-06-30
申请人： Michael Alwais , Michael Peters
发明人： Michael Alwais , Michael Peters
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F12/08 , G06F15/78 , G11C7/22 , G11C11/00 , G11C11/401 , G11C16/04
CPC分类号： G11C7/22 , G06F12/0215 , G06F12/0893 , G06F15/786 , G11C11/005
摘要： An integrated circuit device, and an associated method, in which a logic element, such as a central processing unit, is embedded together with an EDRAM EDRAM (Enhanced Dynamic Random Access Memory) upon a common substrate die. A memory bus interconnects the EDRAM and the logic element. Data thruput rates of memory read and write operations are permitted to be of increased rates relative to the rates permitted of conventional, discrete devices.
摘要翻译：集成电路器件及其相关方法，其中诸如中央处理单元的逻辑元件与共同的衬底管芯上的EDRAM EDRAM（增强型动态随机存取存储器）一起嵌入。存储器总线将EDRAM和逻辑元件相互连接。允许存储器读和写操作的数据猝发速率相对于常规分立器件允许的速率增加。

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