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1. 发明申请

US20110004867A1 AUTOMATED LEVEL-BASED TARGETED TEST CONFIGURATION 失效
标题翻译：自动级别的目标测试配置
公开(公告)号：US20110004867A1
公开(公告)日：2011-01-06
申请号：US12496480
申请日：2009-07-01
申请人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
发明人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
IPC分类号： G06F11/36
CPC分类号： G06F11/3676
摘要： An indication of a change to at least one source file associated with a software build is received via a processor. A set of test levels of a level-based testing suite are sequentially processed, where each test level subsequently processed includes tests with decreasing qualitative testing information relative to tests associated with previously-processed test levels. For each processed test level, at least one test is selected that tests the change to the at least one source file associated with the software build, test coverage relative to a target risk level for the software build is determined for each selected test, and test selection is terminated upon determining that the test coverage for the selected tests at least meets the target risk level for the software build.
摘要翻译：经由处理器接收到与软件构建相关联的至少一个源文件的改变的指示。依次处理基于级别的测试套件的一组测试级别，其中随后处理的每个测试级别包括相对于先前处理的测试级别相关测试的定性测试信息减少的测试。对于每个处理的测试级别，至少选择一个测试来测试与软件构建相关联的至少一个源文件的变化，针对每个所选测试确定针对软件构建的目标风险级别的测试覆盖范围，并且测试确定所选测试的测试覆盖率至少满足软件构建的目标风险级别时终止选择。

2. 发明授权

US08423964B2 Automated level-based targeted test configuration 失效
公开(公告)号：US08423964B2
公开(公告)日：2013-04-16
申请号：US13434748
申请日：2012-03-29
申请人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
发明人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3676
摘要： An indication of a change to at least one source file associated with a software build is received via a processor. A set of test levels of a level-based testing suite are sequentially processed, where each test level subsequently processed includes tests with decreasing qualitative testing information relative to tests associated with previously-processed test levels. For each processed test level, at least one test is selected that tests the change to the at least one source file associated with the software build, test coverage relative to a target risk level for the software build is determined for each selected test, and test selection is terminated upon determining that the test coverage for the selected tests at least meets the target risk level for the software build.

3. 发明申请

US20120192159A1 AUTOMATED LEVEL-BASED TARGETED TEST CONFIGURATION 失效
标题翻译：自动级别的目标测试配置
公开(公告)号：US20120192159A1
公开(公告)日：2012-07-26
申请号：US13434748
申请日：2012-03-29
申请人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
发明人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
IPC分类号： G06F11/36
CPC分类号： G06F11/3676
摘要： An indication of a change to at least one source file associated with a software build is received via a processor. A set of test levels of a level-based testing suite are sequentially processed, where each test level subsequently processed includes tests with decreasing qualitative testing information relative to tests associated with previously-processed test levels. For each processed test level, at least one test is selected that tests the change to the at least one source file associated with the software build, test coverage relative to a target risk level for the software build is determined for each selected test, and test selection is terminated upon determining that the test coverage for the selected tests at least meets the target risk level for the software build.
摘要翻译：经由处理器接收到与软件构建相关联的至少一个源文件的改变的指示。依次处理基于级别的测试套件的一组测试级别，其中随后处理的每个测试级别包括相对于先前处理的测试级别相关测试的定性测试信息减少的测试。对于每个处理的测试级别，至少选择一个测试来测试与软件构建相关联的至少一个源文件的改变，针对每个所选测试确定针对软件构建的目标风险级别的测试覆盖范围，并且测试确定所选测试的测试覆盖率至少满足软件构建的目标风险级别时终止选择。

4. 发明授权

US08423967B2 Automated level-based targeted test configuration 失效
标题翻译：基于级别的自动化目标测试配置
公开(公告)号：US08423967B2
公开(公告)日：2013-04-16
申请号：US12496480
申请日：2009-07-01
申请人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
发明人： Ian G. Holden , Mark R. Hufnagel , Michael T. Peters , Jonathan S. Tilt , Michael J. Triantafelow
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/3676
摘要： An indication of a change to at least one source file associated with a software build is received via a processor. A set of test levels of a level-based testing suite are sequentially processed, where each test level subsequently processed includes tests with decreasing qualitative testing information relative to tests associated with previously-processed test levels. For each processed test level, at least one test is selected that tests the change to the at least one source file associated with the software build, test coverage relative to a target risk level for the software build is determined for each selected test, and test selection is terminated upon determining that the test coverage for the selected tests at least meets the target risk level for the software build.
摘要翻译：经由处理器接收到与软件构建相关联的至少一个源文件的改变的指示。依次处理基于级别的测试套件的一组测试级别，其中随后处理的每个测试级别包括相对于先前处理的测试级别相关测试的定性测试信息减少的测试。对于每个处理的测试级别，至少选择一个测试来测试与软件构建相关联的至少一个源文件的变化，针对每个所选测试确定针对软件构建的目标风险级别的测试覆盖范围，并且测试确定所选测试的测试覆盖率至少满足软件构建的目标风险级别时终止选择。

5. 发明授权

US07533231B1 Method and circuit for increasing the memory access speed of an enhanced synchronous memory 有权
标题翻译：用于增加增强型同步存储器的存储器存取速度的方法和电路
公开(公告)号：US07533231B1
公开(公告)日：2009-05-12
申请号：US10965602
申请日：2004-10-13
申请人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
发明人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
IPC分类号： G06F13/14
CPC分类号： G11C11/4097 , G06F12/0893 , G06F2212/3042 , G11C2207/2245
摘要： A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A number of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, before application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
摘要翻译：用于操作它的存储器和方法提供了增加的数据访问速度。在一个实现中，同步存储器或SDRAM包括具有在相应相对侧上以集合排列的存储器块的中央存储器区域。提供了许多初级感测放大器组，每组都与相应的存储块集合相关联并且位于相邻的位置。在中央存储器区域中提供行缓存，并且行解码器响应于“存储体激活”命令对行地址进行解码，并将数据从解码的行地址移动到与包含解码行的存储器块相关联的初级读出放大器组地址并进入行缓存，然后将“读”命令应用于SDRAM。列解码器响应于“读取”命令解码列地址，并根据解码的列地址从高速缓存读取数据。

6. 发明授权

US06813679B2 Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM 失效
标题翻译：提高增强型同步SDRAM存储器访问速度的方法和电路
公开(公告)号：US06813679B2
公开(公告)日：2004-11-02
申请号：US10178072
申请日：2002-06-20
申请人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
发明人： Kenneth J. Mobley , Michael T. Peters , Michael Schuette
IPC分类号： G06F1208
CPC分类号： G11C11/4097 , G06F12/0893 , G06F2212/3042 , G11C2207/2245
摘要： An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.
摘要翻译：用于操作它的SDRAM和方法提供了增加的数据访问速度。 SDRAM包括具有在相应相对侧上以集合排列的存储块的中央存储器区域。提供了多个原始感测放大器组，每组都与相应的存储器组的集合相关联，并位于其附近。在中央存储器区域中提供行缓存，并且行解码器响应于“存储体激活”命令对行地址进行解码，并将数据从解码的行地址移动到与包含解码行的存储器块相关联的初级读出放大器组地址和行缓存之前，应用一个“读”命令到SDRAM。列解码器响应于“读取”命令解码列地址，并根据解码的列地址从高速缓存读取数据。

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