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1. 发明授权

US07723753B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07723753B2
公开(公告)日：2010-05-25
申请号：US11962169
申请日：2007-12-21
申请人： Kenji Sasaki , Ikuro Akazawa , Yoshinori Imamura , Atsushi Kurokawa , Tatsuhiko Ikeda , Hiroshi Inagawa , Yasunari Umemoto , Isao Obu
发明人： Kenji Sasaki , Ikuro Akazawa , Yoshinori Imamura , Atsushi Kurokawa , Tatsuhiko Ikeda , Hiroshi Inagawa , Yasunari Umemoto , Isao Obu
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L21/8252 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/0605 , H01L29/0619 , H01L29/7371 , H01L29/7811 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05599 , H01L2224/29339 , H01L2224/32225 , H01L2224/45099 , H01L2224/451 , H01L2224/45117 , H01L2224/45144 , H01L2224/45155 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10158 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H01L2924/01032 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.
摘要翻译：在作为半绝缘基板的GaAs衬底中，在元件形成区域中形成异质结双极晶体管（HBT），而在绝缘区域中形成隔离区域。通过将氦引入与HBT的副集电极半导体层和集电体半导体层相同的半导体层中而形成在绝缘区域中的隔离区域。在外围区域中，形成导电层以从保护膜露出并耦合到背面电极。由于将GND电位提供给背面电极，所以导电层固定为GND电位。导电层由与HBT的副集电极半导体层和集电极半导体层相同的半导体层形成。

2. 发明申请

US20080224174A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080224174A1
公开(公告)日：2008-09-18
申请号：US11962169
申请日：2007-12-21
申请人： Kenji SASAKI , Ikuro Akazawa , Yoshinori Imamura , Atsushi Kurokawa , Tatsuhiko Ikeda , Hiroshi Inagawa , Yasunari Umemoto , Isao Obu
发明人： Kenji SASAKI , Ikuro Akazawa , Yoshinori Imamura , Atsushi Kurokawa , Tatsuhiko Ikeda , Hiroshi Inagawa , Yasunari Umemoto , Isao Obu
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L21/8252 , H01L23/481 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/0605 , H01L29/0619 , H01L29/7371 , H01L29/7811 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05599 , H01L2224/29339 , H01L2224/32225 , H01L2224/45099 , H01L2224/451 , H01L2224/45117 , H01L2224/45144 , H01L2224/45155 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01031 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10158 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H01L2924/01032 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.
摘要翻译：提供了允许提高半导体器件的耐湿性的技术。在作为半绝缘基板的GaAs衬底中，在元件形成区域中形成HBT，而在绝缘区域中形成隔离区域。形成在绝缘区域中的隔离区域通过将氦引入与HBT的子集电极半导体层和集电极半导体层相同的半导体层中而形成。在外围区域中，形成导电层以从保护膜露出并耦合到背面电极。由于将GND电位提供给背面电极，所以导电层固定为GND电位。导电层由与HBT的副集电极半导体层和集电极半导体层相同的半导体层形成。

3. 发明申请

US20060138459A1 Semiconductor device, manufacturing method of the same and electronic device 审中-公开
标题翻译：半导体器件及其制造方法及电子器件
公开(公告)号：US20060138459A1
公开(公告)日：2006-06-29
申请号：US11316989
申请日：2005-12-27
申请人： Atsushi Kurokawa , Isao Ohbu , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura
发明人： Atsushi Kurokawa , Isao Ohbu , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura
IPC分类号： H01L31/109
CPC分类号： H01L29/7304 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a semiconductor device equipped with HBTs capable of satisfying both thermal stability and reliability and having improved electrostatic breakdown voltage. The HBT according to the present invention is obtained by successively forming, over the main surface of a substrate made of a compound semiconductor, a sub-collector layer, a collector layer, a base layer, an emitter layer, a collector electrode electrically connected to the collector layer, a base electrode electrically connected to the base layer, an emitter mesa layer formed over the emitter layer and electrically connected to the emitter layer, and an emitter electrode electrically connected to the emitter mesa layer. The emitter mesa layer has a semiconductor layer made of an n type GaAs layer, a high concentration semiconductor layer made of an n+ type GaAs layer over the semiconductor layer and a ballast resistor layer made of an n type InGaAs layer over the high concentration semiconductor layer.
摘要翻译：提供了配备能够满足热稳定性和可靠性并具有改善的静电击穿电压的HBT的半导体器件。根据本发明的HBT是通过在由化合物半导体制成的衬底的主表面上连续形成子集电极层，集电极层，基极层，发射极层，集电极，电连接到集电极层，电连接到基极层的基极，在发射极层上形成并电连接到发射极层的发射极台面层和电连接到发射极台面层的发射极。发射极台面层具有由n型GaAs层构成的半导体层，在半导体层上形成由n + +型GaAs层构成的高浓度半导体层和由n型GaAs层制成的镇流电阻层 InGaAs层在高浓度半导体层上。

4. 发明申请

US20090194792A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090194792A1
公开(公告)日：2009-08-06
申请号：US12413010
申请日：2009-03-27
申请人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
发明人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
IPC分类号： H01L27/082 , H01L23/498
CPC分类号： H01L29/4933 , H01L21/84 , H01L23/4824 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L29/456 , H01L29/7835 , H01L2224/1403 , H01L2224/16235 , H01L2224/1703 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.
摘要翻译：半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。连接到GND的外部配线的多个通孔形成为穿透布线基板。包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。发射极电极沿HBT排列的方向延伸。第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

5. 发明申请

US20050258452A1 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050258452A1
公开(公告)日：2005-11-24
申请号：US11108729
申请日：2005-04-19
申请人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
发明人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
IPC分类号： H01L21/28 , H01L21/331 , H01L21/8222 , H01L21/84 , H01L23/34 , H01L23/482 , H01L23/498 , H01L25/065 , H01L25/07 , H01L25/16 , H01L25/18 , H01L27/082 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/737 , H01L29/739 , H01L29/78
CPC分类号： H01L29/4933 , H01L21/84 , H01L23/4824 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L29/456 , H01L29/7835 , H01L2224/1403 , H01L2224/16235 , H01L2224/1703 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.
摘要翻译：半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。连接到GND的外部配线的多个通孔形成为穿透布线基板。包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。发射极电极沿HBT排列的方向延伸。第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

6. 发明授权

US07511315B2 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07511315B2
公开(公告)日：2009-03-31
申请号：US11108729
申请日：2005-04-19
申请人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
发明人： Satoru Konishi , Tsuneo Endo , Hirokazu Nakajima , Yasunari Umemoto , Satoshi Sasaki , Chushiro Kusano , Yoshinori Imamura , Atsushi Kurokawa
IPC分类号： H01L21/00 , H01L29/34 , H01L23/48 , H01L21/4763
CPC分类号： H01L29/4933 , H01L21/84 , H01L23/4824 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L29/456 , H01L29/7835 , H01L2224/1403 , H01L2224/16235 , H01L2224/1703 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/49175 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.
摘要翻译：半导体器件具有在布线基板的下表面上形成的用于GND的外部布线。连接到GND的外部配线的多个通孔形成为穿透布线基板。包括HBT的高功率的第一半导体芯片安装在布线基板的主表面上。第一半导体芯片的发射极电极与形成在第一半导体芯片中的多个HBT的发射极共同连接。发射极电极沿HBT排列的方向延伸。第一半导体芯片安装在布线基板上，使得多个通孔与发射极电极连接。散热值比第一半导体芯片低的第二半导体芯片安装在第一半导体芯片上。

7. 发明申请

US20060057789A1 Method for manufacturing semiconductor device 失效
公开(公告)号：US20060057789A1
公开(公告)日：2006-03-16
申请号：US11266259
申请日：2005-11-04
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21/338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.

8. 发明授权

US07214558B2 Method for forming patterns on a semiconductor device using a lift off technique 失效
标题翻译：使用剥离技术在半导体器件上形成图案的方法
公开(公告)号：US07214558B2
公开(公告)日：2007-05-08
申请号：US11257060
申请日：2005-10-25
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： H01L21/00 , H01L21/8235
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译：提供了改进双极晶体管的性质的技术。具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜，随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从基板的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。

9. 发明授权

US06649458B2 Method for manufacturing semiconductor device with hetero junction bipolar transistor 有权
标题翻译：具有异质结双极晶体管的半导体器件的制造方法
公开(公告)号：US06649458B2
公开(公告)日：2003-11-18
申请号：US10347806
申请日：2003-01-22
申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
发明人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
IPC分类号： H01L21338
CPC分类号： H01L29/66143 , H01L21/8252 , H01L27/0605 , H01L27/0652 , H01L27/0658 , H01L27/0664 , H01L29/475 , H01L29/66212 , H01L29/66318 , H01L29/7371
摘要： The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
摘要翻译：本发明在具有异质结双极晶体管（HBT），肖特基二极管和电阻元件的半导体器件的制造方法中实现了制造成品率的提高和制造成本的降低。本发明涉及一种半导体器件的制造方法，其中，在半导体器件的一个表面上依次形成成为副集电极层，集电极层，基极层，宽间隙发射极层和发射极层的各个半导体层半导体衬底，然后处理各个半导体层以形成异质结双极晶体管，肖特基二极管和电阻元件。使用相同的材料（例如WSiN）同时形成异质结双极晶体管的发射极，肖特基二极管的肖特基电极和电阻元件的电阻膜。因此，可以减少工时，并且可以降低半导体器件的制造成本。

10. 发明授权

US07378690B2 Method for forming patterns on a semiconductor device using a lift off technique 失效
标题翻译：使用剥离技术在半导体器件上形成图案的方法
公开(公告)号：US07378690B2
公开(公告)日：2008-05-27
申请号：US11727246
申请日：2007-03-26
申请人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
发明人： Atsushi Kurokawa , Hiroshi Inagawa , Toshiaki Kitahara , Yoshinori Imamura
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66318 , H01L29/0657 , H01L29/41708 , H01L29/42304 , H01L29/7371
摘要： Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.
摘要翻译：提供了改进双极晶体管的性质的技术。具体地说，通过剥离法在基台周围形成集电极时，在区域OA1的外周与形成有基台面4a的区域之间的连接部分上形成抗蚀剂膜，随后在衬底的整个表面上依次形成金锗（AuGe），镍（Ni）和Au，使得它们的堆叠膜不会变成隔离图案。结果，基底台面4a上的层叠膜在区域OA1的外周与层叠膜连接，有利于层叠膜在基台面4a上的剥离。此外，通过使用几乎不与n型GaAs层反应的诸如WSi的材料形成背面通孔电极来减少形成从衬底的背面延伸到背面通孔电极的通孔形成侧面蚀刻，或 n型InGaAs层。

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